CDC3RL02YFPR ,Dual-Channel Square/Sine-to-Square Wave Clock Buffer 8-DSBGA -40 to 85Features 3 DescriptionThe CDC3RL02 is a two-channel clock fan-out buffer1• Low Additive Noise:and i ..
CDC421A100RGET ,Fully Integrated Fixed Frequency Low-Jitter Crystal Oscillator Clock Generator 24-VQFN -40 to 85FEATURES APPLICATIONS• Low-Cost, Low-Jitter Frequency Multiplier2• Single 3.3-V Supply• High-Perfor ..
CDC421A156RGET ,Fully Integrated Fixed Frequency Low-Jitter Crystal Oscillator Clock Generator 24-VQFN -55 to 125FEATURES APPLICATIONS• Low-Cost, Low-Jitter Frequency Multiplier2• Single 3.3-V Supply• High-Perfor ..
CDC509PWR ,3.3V Phase Lock Loop Clock Driverblock diagram111G31Y041Y151Y281Y391Y4142G212Y0202Y11724 2Y2CLKÁÁÁÁÁÁPLL1613ÁÁÁÁÁÁ 2Y3FBIN12FBOUT23A ..
CDC516DGG ,3.3V Phase Lock Loop Clock Driver with 3-State Outputs SCAS575B − JULY 1996 − REVISED DECEMBER 2004DGG PACKAGE Use ..
CDC516DGGR ,3.3V Phase Lock Loop Clock Driver with 3-State Outputs SCAS575B − JULY 1996 − REVISED DECEMBER 2004DGG PACKAGE Use ..
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CDC3RL02YFPR
Dual-Channel Square/Sine-to-Square Wave Clock Buffer
VBATT
GND
MCLK_IN
LDO
Switch/
DecoderCC
VLDO
CLK_OUT1
CLK_REQ1
CLK_OUT2
CLK_REQ2EN
VCC
CDC3RL02SCHS371D –NOVEMBER 2009–REVISED APRIL 2017
CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer Features Low Additive Noise: –149 dBc/Hzat 10-kHz Offset Phase Noise 0.37ps (RMS) Output Jitter Limited Output Slew Rate for EMI Reduction
(1-to 5-ns Rise/Fall Timefor 10-pFto 50-pF
Loads) Adaptive Output Stage Controls Reflection Regulated 1.8-V Externally Available I/O Supply Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP
(0.8 mm× 1.6 mm) ESD Performance Exceeds JESD22 2000-V Human-Body Model (A114-A) 1000-V Charged-Device Model
(JESD22-C101-A LevelIII)
Applications Cellular Phones Global Positioning Systems (GPS) Wireless LAN FM Radio WiMAX W-BT
Simplified Block Diagram DescriptionThe CDC3RL02isa two-channel clock fan-out buffer
andis ideal for usein portable end-equipment, such mobile phones, that require clock buffering with
minimal additive phase noise and fan-out capabilities. buffers a single master clock, such as a
temperature compensated crystal oscillator (TCXO) multiple peripherals. The device has two clock
request inputs (CLK_REQ1 and CLK_REQ2), eachof
which enablea single clock output.
The CDC3RL02 accepts squareor sine wavesat the
master clock input (MCLK_IN), eliminating the need
for an AC coupling capacitor. The smallest
acceptable sine waveisa 0.3-V signal (peak-to-
peak). CDC3RL02 has been designed to offer
minimal channel-to-channel skew, additive output
jitter, and additive phase noise. The adaptive clock
output buffers offer controlled slew-rate overa wide
capacitive loading range which minimizes EMI
emissions, maintains signal integrity, and minimizes
ringing caused by signal reflections on the clock
distribution lines.
The CDC3RL02 has an integrated Low-Drop-Out
(LDO) voltage regulator which accepts input voltages
from 2.3Vto 5.5V and outputs 1.8V, 50 mA. This
1.8-V supply is externally available to provide
regulated power to peripheral devices such asa
TCXO.
The CDC3RL02is offeredina 0.4-mm pitch wafer-
level chip-scale (WCSP) package (0.8 mm× 1.6 mm)
and is optimized for very low standby current
consumption.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
