CDC351DWR ,1-Line to 10-Line 3.3V Clock Driver with Tri-State OutputsSCAS441DFEBRUARY 1994REVISED OCTOBER 2003ALOGIC SYMBOL5ENOE23Y121Y219Y318Y4166Y5A14Y611Y79Y84Y92Y ..
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CDC351-CDC351DB-CDC351DBLE-CDC351DBR-CDC351DBRG4-CDC351DW-CDC351DWR-CDC351DWRG4
1-Line to 10-Line 3.3V Clock Driver with Tri-State Outputs
www.ti.comGND
Y10
VCC
VCC
GND
GND
VCC
GND
GND
VCC
GND
DB OR DW PACKAGE
(TOP VIEW)
CDC351. CDC351I
1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTSSCAS441DFEBRUARY 1994REVISED OCTOBER 2003
FEATURES Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications Operatesat 3.3-V VCC LVTTL-Compatible Inputs and Outputs Supports Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC) Distributes One Clock Inputto Ten Outputs Distributed VCC and Ground Pins Reduce
Switching Noise High-Drive Outputs (32-mA IOH, 32-mA IOL) State-of-the-Art EPIC-IIB BiCMOS Design
Significantly Reduces Power Dissipation Package Options Include Plastic
Small-Outline (DW) and Shrink Small-Outline
(DB) Packages
DESCRIPTIONThe CDC351isa high-performance clock-driver circuit that distributes one input (A)to ten outputs (Y) with minimum
skew for clock distribution. The output-enable (OE) input disables the outputstoa high-impedance state. The
CDC351 operatesat nominal 3.3-V VCC.
The propagation delays are adjustedat the factory using theP0 andP1 pins. The factory adjustments ensure that the
part-to-part skewis minimized andis kept withina specified window. PinsP0 andP1 are not intended for customer
use and shouldbe connectedto GND.
FUNCTION TABLEINPUTS OUTPUTSA OE H Z H Z L L L H
AVAILABLE OPTIONS Shrink Small-Outline Package (DB)(1)
Small-Outline Package (DW)(1)0°Cto 70°C CDC351DB CDC351DW 40°Cto 85°C CDC351IDB CDC351IDW
(1) This packageis available tape and reel. Orderby addinganRtothe orderable part number (e.g., CDC351DBR).
