CDC337 ,1-To-8 (4 Same Frequency, 4 Divide-By-2) Clock Driver With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CDC337DW ,1-To-8 (4 Same Frequency, 4 Divide-By-2) Clock Driver With Clearmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CDC337DWR ,1-To-8 (4 Same Frequency, 4 Divide-By-2) Clock Driver With Clear CDC337 CLOCK DRIVERWITH 3-STATE OUTPUTSSCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 DW PACKAGE* ..
CDC339 ,1-To-8 (4 Same Frequency, 4 Divide-By-2) Clock Driver With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CDC339DB ,1-To-8 (4 Same Frequency, 4 Divide-By-2) Clock Driver With Clearlogic diagram (positive logic)5OE5OE EN18Y118Y120Y21620CLK 1Y2Y33Y4131Q1Y311TQ2106 Q3CLR R 83Q4Y416 ..
CDC339DBR , CLOCK DRIVER WITH 3-STATE OUTPUTS
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CDC337-CDC337DW-CDC337DWR
1-To-8 (4 Same Frequency, 4 Divide-By-2) Clock Driver With Clear
Distributes One Clock Input to EightOutputs
– Four Same-Frequency Outputs
– Four Half-Frequency Outputs Distributed VCC and Ground Pins Reduce
Switching Noise High-Drive Outputs (–48-mA IOH,
48-mA IOL) State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation Package Options Include Plastic
Small-Outline (DW)
descriptionThe CDC337 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring
synchronized output signals at both the clock frequency and one-half the clock frequency. The four Y outputs
switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the
frequency of CLK.
When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the
Q outputs toggle on low-to-high transitions at CLK. Taking CLR low asynchronously resets the Q outputs to the
low level. When OE is high, the outputs are in the high-impedance state.
The CDC337 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE The level of the Q outputs before the
indicated steady-state input conditions were
established
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VCC
CLR
VCC
GND
VCC
CLK
GND
VCC
GND
