CDC319DBR ,1-Line to 10-Line Clock Driver with I2C Control InterfaceCDC3191-LINE TO 10-LINE CLOCK DRIVER2WITH I C CONTROL INTERFACESCAS590A – DECEMBER 1997 – REVISED O ..
CDC319DBRG4 ,1-Line to 10-Line Clock Driver with I2C Control Interface 28-SSOP 0 to 70CDC3191-LINE TO 10-LINE CLOCK DRIVER2WITH I C CONTROL INTERFACESCAS590A – DECEMBER 1997 – REVISED O ..
CDC319DBRG4 ,1-Line to 10-Line Clock Driver with I2C Control Interface 28-SSOP 0 to 70logic diagram (positive logic)20OE14SDATA2I C102 RegisterI C /Space2, 3, 6, 7151Y0–1Y3SCLOCK22, 23, ..
CDC3231G , CDC 3231G ARM7-Based Car Dashboard Controller
CDC3257G , CDC 3257G ARM7-Based Car Dashboard Controller
CDC328 ,1-Line To 6-Line Clock Driver With Selectable Polarity 16-SOIC
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CDC319-CDC319DB-CDC319DBG4-CDC319DBR-CDC319DBRG4
1-Line to 10-Line Clock Driver with I2C Control Interface
sk(p) Supports up to Two Unbuffered SDRAMDIMMs (Dual Inline Memory Modules) I2 C Serial Interface Provides Individual
Enable Control for Each Output Operates at 3.3 V Distributed VCC and Ground Pins Reduce
Switching Noise ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015 Packaged in 28-Pin Shrink Small Outline
(DB) Package
descriptionThe CDC319 is a high-performance clock buffer that distributes one input (A) to 10 outputs (Y) with minimum
skew for clock distribution. The CDC319 operates from a 3.3-V power supply, and is characterized for operation
from 0°C to 70°C.
The device provides a standard mode (100K-bits/s) I2C serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs
(SDATA and SCLOCK) provide integrated pullup resistors (typically 140 kΩ) and are 5-V tolerant.
Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,
random access of the registers is not supported).
The CDC319 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
VCC
1Y2
1Y3
GND
VCC
3Y0
GNDCC
SDATA
GND
VCC
2Y1
2Y0
GND
VCC
3Y1
GND
GND
SCLOCK
