CDC318ADLRG4 ,1-Line To 18-Line Clock Driver With I2C Control Interface 48-SSOP SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2 ..
CDC318DL ,1-Line To 18-Line Clock Driver With I2C Control Interface 48-SSOP
CDC319 ,1-Line to 10-Line Clock Driver with I2C Control Interfacemaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CDC319DB ,1-Line to 10-Line Clock Driver with I2C Control Interfacelogic diagram (positive logic)20OE14SDATA2I C102 RegisterI C /Space2, 3, 6, 7151Y0–1Y3SCLOCK22, 23, ..
CDC319DBG4 ,1-Line to 10-Line Clock Driver with I2C Control Interface 28-SSOP 0 to 70maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CDC319DBR ,1-Line to 10-Line Clock Driver with I2C Control InterfaceCDC3191-LINE TO 10-LINE CLOCK DRIVER2WITH I C CONTROL INTERFACESCAS590A – DECEMBER 1997 – REVISED O ..
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CDC318A-CDC318ADL-CDC318ADLRG4
1-Line To 18-Line Clock Driver With I2C Control Interface
Supports up to Four Unbuffered SDRAMDual Inline Memory Modules (DIMMs) I2C Serial Interface Provides Individual
Enable Control for Each Output Operates at 3.3 V Distributed VCC and Ground Pins Reduce
Switching Noise 100-MHz Operation ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015 Packaged in 48-Pin Shrink Small Outline
(DL) Package
descriptionThe CDC318A is a high-performance clock buffer
designed to distribute high-speed clocks in PC
applications. This device distributes one input (A)
to 18 outputs (Y) with minimum skew for clock
distribution. The CDC318A operates from a 3.3-V
power supply. It is characterized for operation
from 0°C to 70°C.
This device has been designed with consideration
for optimized EMI performance. Depending on the
application layout, damping resistors in series to
the clock outputs (like proposed in the PC100
specification) may not be needed in most cases.
The device provides a standard mode (100K-bits/s) I2 C serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the I2 C device address table. Both of the I2 C inputs
(SDATA and SCLOCK) are 5-V tolerant and provide integrated pullup resistors (typically 140 kΩ).
Three 8-bit I2 C registers provide individual enable control for each of the outputs. All outputs default to enabled
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,
random access of the registers is not supported).
The CDC318A provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
