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CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
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CL431 , Precision Adjustable Shunt Reference
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CDC2536-CDC2536DB-CDC2536DBG4-CDC2536DBR-CDC2536DL-CDC2536DLR
3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options
FEATURESAVCC
AGND
CLKIN
SEL
GND
1Y1
VCC
GND
1Y2
VCC
GND
1Y3
VCC
AVCC
AGND
FBIN
TEST
CLR
VCC
2Y1
GND
VCC
2Y2
GND
VCC
2Y3
GND
DB PACKAGE
(TOP VIEW)
DESCRIPTION
3.3-V LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS Low Output for Clock-Distribution and
Clock-Generation Applications Operatesat VCC Distributes Clock Inputto Six Outputs One Select Input Configures Three Outputsto
Operateat One-Halfor Double the Input
Frequency No External Network Required On-Chip Series Damping Resistors External Feedback Pin (FBIN)Is Usedto
Synchronize Outputsto the Clock Input Application Synchronous DRAM,
High-Speed TTL-Compatible Inputs and Outputs Outputs Drive Parallel-Terminated
Transmission State-of-the-Art EPIC-IIB™ BiCMOS Design
Significantly Power Dissipation Distributed and Ground Pins Reduce
Switching Noise Packagedin 28-Pin Shrink
Small-OutlineThe CDC2536is high-performance, low-skew, low-jitter driver.It usesa phase-lock loop (PLL) to
precisely align,in frequency and phase, the clock output signalsto the clock input (CLKIN) signal.Itis
specifically designed for use with synchronous DRAMs and microprocessors operatingat speeds from MHzto 100 or downto 25 MHz on outputs configured as half-frequency outputs. The CDC2536
operatesat 3.3-V andis designedto drivea 50-W transmission line. The CDC2536 also provides on-chip
series-damping resistors, eliminating the need for external termination components.
The feedback (FBIN) inputis usedto synchronize the output clocksin frequency and phaseto the input clock
(CLKIN). Oneof six output clocks mustbe fed backto FBIN for the PLLto maintain synchronization between
CLKIN and the outputs. The output usedas the feedback pin synchronizedto the same frequencyas CLKIN.
TheY outputs can configuredto switchin phase andat the frequencyas CLKIN. The select (SEL) input threeto operateat one-halfor double CLKIN frequency, dependingon which pinis fed (see1 and 2). All output signal duty are adjustedto 50% independentof the duty input
