CDC2510BPWR ,3.3-V Phase-Lock Loop Clock Driverblock diagram11G31Y041Y151Y281Y391Y4151Y5161Y617241Y7CLKPLLÁÁÁÁÁÁ20131Y8FBIN211Y923AVCC12FBOUTAVAIL ..
CDC2510C ,3.3-V Phase-Lock Loop Clock Driver SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004PW PACKAGE ..
CDC2510CPW ,3.3-V Phase-Lock Loop Clock Driver SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004PW PACKAGE ..
CDC2510CPWG4 ,3.3-V Phase-Lock Loop Clock Driver 24-TSSOP maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, A ..
CDC2510CPWR ,3.3-V Phase-Lock Loop Clock Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, A ..
CDC2510CPWRG4 ,3.3-V Phase-Lock Loop Clock Driver 24-TSSOP block diagram11G31Y041Y151Y281Y391Y4151Y5161Y617241Y7CLKÁÁÁÁÁÁPLL20131Y8ÁÁÁÁÁÁFBIN211Y923AVCC12FBOU ..
CL2431VS , Precision Adjustable Shunt Reference
CL-25 , Simple 90V, 25mA, Temperature Compensated, Constant Current, LED Driver IC
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CDC2510BPWR
3.3-V Phase-Lock Loop Clock Driver
Operating Frequency 25 MHz to 125 MHz tPhase Error Minus Jitter at 66 MHz to100 MHz Is ±150 ps Jitter (pk − pk) at 66 MHz to 100 MHz is±80ps
Jitter (cyc − cyc) at 66 MHz to 100 MHz is
|100 ps| Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications Distributes One Clock Input to One Bank of
Ten Outputs Separate Output Enable for Each Output
Bank External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3-V
descriptionThe CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDC2510B operates at 3.3-V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510B does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510B requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.CC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
VCC
FBIN
1Y0
1Y1
1Y2
GNDCC
FBOUT
