CDC2509CPWR G4 ,1-to-9 PLL Clock Driver 24-TSSOP block diagram111G31Y041Y151Y281Y391Y4142G212Y0202Y117242Y2CLKPLL16ÁÁÁÁÁÁ132Y3FBIN12FBOUT23AVCCAVAIL ..
CDC2509CPWRG4 ,1-to-9 PLL Clock Driver 24-TSSOP block diagram111G31Y041Y151Y281Y391Y4142G212Y0202Y117242Y2CLKPLL16ÁÁÁÁÁÁ132Y3FBIN12FBOUT23AVCCAVAIL ..
CDC2509PW , 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2509PW , 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510BPWR ,3.3-V Phase-Lock Loop Clock Driverblock diagram11G31Y041Y151Y281Y391Y4151Y5161Y617241Y7CLKPLLÁÁÁÁÁÁ20131Y8FBIN211Y923AVCC12FBOUTAVAIL ..
CDC2510C ,3.3-V Phase-Lock Loop Clock Driver SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004PW PACKAGE ..
CL2431VS , Precision Adjustable Shunt Reference
CL-25 , Simple 90V, 25mA, Temperature Compensated, Constant Current, LED Driver IC
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CDC2509CPW-CDC2509CPWR-CDC2509CPWR G4-CDC2509CPWRG4
1-to-9 PLL Clock Driver
Operating Frequency 25 MHz to 125 MHz Static tPhase Error Distribution at 66MHz to100 MHz is ±150 ps Drop-In Replacement for TI CDC2509A With
Enhanced Performance Jitter (cyc − cyc) at 66 MHz to 100 MHz is
|100 ps| Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs Separate Output Enable for Each Output
Bank External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3 V
descriptionThe CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDC2509C operates at 3.3 V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled
or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in
phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2509C does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2509C requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDC2509C is characterized for operation from 0°C to 85°C.
1Y0
1Y1
1Y2
GND
GND
1Y3CC
FBOUT
