CDC2351QDBR ,1-Line to 10-Line 3.3V Clock Driver with Tri-State OutputsCDC23511-LINE TO 10-LINE CLOCK DRIVERWITH 3-STATE OUTPUTSSCAS442D – FEBRUARY 1994 – REVISED SEPTEMB ..
CDC2509B ,1-to-9 PLL Clock Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CDC2509BPW ,3.3-V PHASE-LOCK LOOP CLOCK DRIVERmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CDC2509BPWG4 ,1-to-9 PLL Clock Driver 24-TSSOP 0 to 70 SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004PW PACKAGE ..
CDC2509BPWR ,1-to-9 PLL Clock Driver SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004PW PACKAGE ..
CDC2509BPWR ,1-to-9 PLL Clock Driverblock diagram111G31Y041Y151Y281Y391Y4142G212Y0202Y1 17242Y2CLKPLLÁÁÁÁÁÁ 16132Y3FBIN12FBOUT23AVCCAVA ..
CL2431VS , Precision Adjustable Shunt Reference
CL-25 , Simple 90V, 25mA, Temperature Compensated, Constant Current, LED Driver IC
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CDC2351QDBR
Automotive 1-Line to 10-Line Clock Driver With 3-State Outputs 24-SSOP -40 to 125
Supports Mixed-Mode Signal Operation(5-V Input and Output Voltages With 3.3-V
VCC) Distributes One Clock Input to Ten Outputs Outputs Have Internal Series Damping
Resistor to Reduce Transmission Line
Effects Distributed VCC and Ground Pins Reduce
Switching Noise State-of-the-Art EPIC-II B BiCMOS Design
Significantly Reduces Power Dissipation Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
descriptionThe CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with
minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance
state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351
operates at nominal 3.3-V VCC.
The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure
that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended
for customer use and should be connected to GND.
The CDC2351 is characterized for operation from 0°C to 70°C. The CDC2351Q is characterized for operation
over the full automotive temperature range of –40°C to 125°C.
FUNCTION TABLEPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VCC
GND
GND
GND
VCC
GND
