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CDC111FNTIN/a30avai3.3V LVPECL Differential Clock Driver


CDC111FN ,3.3V LVPECL Differential Clock Driver CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUS ..
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CDC111FN
3.3V LVPECL Differential Clock Driver
Differential Clock Outputs Output Reference Voltage, VREF, Allows
Distribution From a Single-Ended Clock
Input
Single-Ended LVPECL-Compatible Output
Enable
Packaged in Plastic Chip Carrier

description

The differential LVPECL clock-driver circuit
distributes one pair of differential LVPECL clock
inputs (CLKIN, CLKIN) to nine pairs of differential
clock (Y , Y) outputs with minimum skew for clock
distribution. It is specifically designed for driving
50-W transmission lines.
When the output-enable (OE) is low, the nine differential outputs switch at the same frequency as the differential
clock inputs. When OE is high, the nine differential outputs are in static states (Y outputs are in the low state,
Y outputs are in the high state).
The VREF output can be strapped to the CLKIN input for a single-ended CLKIN input.
The CDC111 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VCC0
VCC0Y4
V Y3Y3
CC0
NC – No internal connection
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