CD74HCT74M ,High Speed CMOS Logic Dual Positive-Edge-Triggered D Flip-Flops with Set and ResetCD54HC74, CD74HC74,CD54HCT74, CD74HCT74Data sheet acquired from Harris SemiconductorSCHS124DDual D ..
CD74HCT74M ,High Speed CMOS Logic Dual Positive-Edge-Triggered D Flip-Flops with Set and ResetFeatures Description• Hysteresis on Clock Inputs for Improved Noise The ’HC74 and ’HCT74 utilize si ..
CD74HCT74M96 ,High Speed CMOS Logic Dual Positive-Edge-Triggered D Flip-Flops with Set and ResetCD54HC74, CD74HC74,CD54HCT74, CD74HCT74Data sheet acquired from Harris SemiconductorSCHS124DDual D ..
CD74HCT75E ,High Speed CMOS Logic Dual 2-Bit Bistable Transparent LatchMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD74HCT75E ,High Speed CMOS Logic Dual 2-Bit Bistable Transparent LatchCD54HC75, CD74HC75,CD54HCT75, CD74HCT75Data sheet acquired from Harris SemiconductorSCHS135FDual 2- ..
CD74HCT75M ,High Speed CMOS Logic Dual 2-Bit Bistable Transparent LatchFeatures Description• True and Complementary Outputs The ’HC75 and ’HCT75 are dual 2-bit bistable t ..
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CD74HCT74E-CD74HCT74M-CD74HCT74M96
High Speed CMOS Logic Dual Positive-Edge-Triggered D Flip-Flops with Set and Reset
CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 SCHS124D Dual D Flip-Flop with Set and Reset January 1998 - Revised September 2003 Positive-Edge Trigger Features Description • Hysteresis on Clock Inputs for Improved Noise The ’HC74 and ’HCT74 utilize silicon gate CMOS technology Immunity and Increased Input Rise and Fall Times to achieve operating speeds equivalent to LSTTL parts. [ /Title They exhibit the low power consumption of standard CMOS • Asynchronous Set and Reset (CD54H integrated circuits, together with the ability to drive 10 LSTTL loads. • Complementary Outputs C74, CD74H This flip-flop has independent DATA, SET, RESET and • Buffered Inputs CLOCK inputs and Q and Q outputs. The logic level present C74, = 50MHz at V = 5V, C = 15pF, • Typical f MAX CC L at the data input is transferred to the output during the o CD74H T = 25 C A positive-going transition of the clock pulse. SET and RESET CT74) are independent of the clock and are accomplished by a low • Fanout (Over Temperature Range) level at the appropriate input. /Subject - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads (Dual D - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible with the standard LS logic family. Flip- o o • Wide Operating Temperature Range . . . -55 C to 125 C Flop Ordering Information • Balanced Propagation Delay and Transition Times with Set TEMP. RANGE • Significant Power Reduction Compared to LSTTL o PART NUMBER ( C) PACKAGE Logic ICs CD54HC74F3A -55 to 125 14 Ld CERDIP • HC Types CD54HCT74F3A -55 to 125 14 Ld CERDIP - 2V to 6V Operation - High Noise Immunity: N = 30%, N = 30% of V CD74HC74E -55 to 125 14 Ld PDIP IL IH CC at V = 5V CC CD74HC74M -55 to 125 14 Ld SOIC • HCT Types CD74HC74MT -55 to 125 14 Ld SOIC - 4.5V to 5.5V Operation CD74HC74M96 -55 to 125 14 Ld SOIC - Direct LSTTL Input Logic Compatibility, CD74HCT74E -55 to 125 14 Ld PDIP = 0.8V (Max), V = 2V (Min) V IL IH CD74HCT74M -55 to 125 14 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HCT74MT -55 to 125 14 Ld SOIC CD74HCT74M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
