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CD74HCT563EHARRISN/a7avaiHigh Speed CMOS Logic Octal Transparent Inverting Latches with 3-State Outputs
CD74HCT563MTIN/a100avaiHigh Speed CMOS Logic Octal Transparent Inverting Latches with 3-State Outputs


CD74HCT563M ,High Speed CMOS Logic Octal Transparent Inverting Latches with 3-State OutputsFeatures Description• Common Latch-Enable Control The ’HC533, ’HCT533, ’HC563, and CD74HCT563 arehi ..
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CD74HCT573E ,High Speed CMOS Logic Octal Transparent Latches with 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74HCT573M ,High Speed CMOS Logic Octal Transparent Latches with 3-State Outputslogic diagram (positive logic)1OE11LEC1 191Q21D 1DTo Seven Other Channels†absolute
CD74HCT573M96 ,High Speed CMOS Logic Octal Transparent Latches with 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
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CD74HCT563E-CD74HCT563M
High Speed CMOS Logic Octal Transparent Inverting Latches with 3-State Outputs
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 SCHS187C High-Speed CMOS Logic Octal Inverting January 1998 - Revised July 2003 Transparent Latch, Three-State Outputs Features Description • Common Latch-Enable Control The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high-speed Octal Transparent Latches manufactured with • Common Three-State Output Enable Control [ /Title silicon gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well as (CD74H • Buffered Inputs the ability to drive 15 LSTTL devices. C533, • Three-State Outputs The outputs are transparent to the inputs when the latch CD74H • Bus Line Driving Capacity enable (LE) is high. When the latch enable (LE) goes low the CT533, data is latched. The output enable (OE) controls the = 5V, • Typical Propagation Delay = 13ns at V CC CD74H o three-state outputs. When the output enable (OE) is high the C = 15pF, T = 25 C (Data to Output) L A C563, outputs are in the high impedance state. The latch operation • Fanout (Over Temperature Range) is independent of the state of the output enable. CD74H - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads CT563) The ’HC533 and ’HCT533 are identical in function to the - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads ’HC563 and CD74HCT563 but have different pinouts. The /Subject o o • Wide Operating Temperature Range . . . -55 C to 125 C ’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373; (High the latter are non-inverting types. • Balanced Propagation Delay and Transition Times Speed Ordering Information • Significant Power Reduction Compared to LSTTL Logic ICs TEMP. RANGE o • HC Types PART NUMBER ( C) PACKAGE - 2V to 6V Operation CD54HC533F3A -55 to 125 20 Ld CERDIP - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CD54HC563F3A -55 to 125 20 Ld CERDIP CC CD54HCT533F3A -55 to 125 20 Ld CERDIP • HCT Types - 4.5V to 5.5V Operation CD74HC533E -55 to 125 20 Ld PDIP - Direct LSTTL Input Logic Compatibility, CD74HC563E -55 to 125 20 Ld PDIP V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1μA at V , V CD74HC563M -55 to 125 20 Ld SOIC l OL OH CD74HCT533E -55 to 125 20 Ld PDIP CD74HCT563E -55 to 125 20 Ld PDIP CD74HCT563M -55 to 125 20 Ld SOIC CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
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