CD74HCT273M96 ,High Speed CMOS Logic Octal D-Type Flip-Flop with ResetFeatures Description• Common Clock and Asynchronous Master Reset The ’HC273 and ’HCT273 high speed ..
CD74HCT273M96 ,High Speed CMOS Logic Octal D-Type Flip-Flop with ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HCT273M96 ,High Speed CMOS Logic Octal D-Type Flip-Flop with ResetFeatures Description• Common Clock and Asynchronous Master Reset The ’HC273 and ’HCT273 high speed ..
CD74HCT27E ,High Speed CMOS Logic Triple 3-Input NOR GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HCT27M ,High Speed CMOS Logic Triple 3-Input NOR GatesFeatures Description• Buffered Inputs The ’HC27 and ’HCT27 logic gates utilize silicon gate CMOStec ..
CD74HCT27M96 ,High Speed CMOS Logic Triple 3-Input NOR GatesCD54HC27, CD74HC27,CD54HCT27, CD74HCT27Data sheet acquired from Harris SemiconductorSCHS132CHigh-Sp ..
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CD74HCT273E-CD74HCT273M-CD74HCT273M96
High Speed CMOS Logic Octal D-Type Flip-Flop with Reset
CD54HC273, CD74HC273, CD54HCT273, CD74HCT273 SCHS174B High-Speed CMOS Logic February 1998 - Revised May 2003 Octal D-Type Flip-Flop with Reset Features Description • Common Clock and Asynchronous Master Reset The ’HC273 and ’HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicon-gate • Positive Edge Triggering [ /Title CMOS technology. They possess the low power consumption of standard CMOS integrated circuits. (CD74 • Buffered Inputs HC273 Information at the D inputis transferred to the Q outputs on • Fanout (Over Temperature Range) the positive-going edge of the clock pulse. All eight flip-flops , - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads are controlled by a common clock (CP) and a common reset - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD74 (MR). Resetting is accomplished by a low voltage level o o HCT27 • Wide Operating Temperature Range . . . -55 C to 125 C independent of the clock. All eight Q outputs are reset to a 3) logic 0. • Balanced Propagation Delay and Transition Times /Sub- Ordering Information • Significant Power Reduction Compared to LSTTL ject Logic ICs o PART NUMBER TEMP. RANGE ( C) PACKAGE (High • HC Types CD54HC273F3A -55 to 125 20 Ld CERDIP Speed - 2V to 6V Operation - High Noise Immunity: N = 30%, N = 30% of V CMOS CD74HC273E -55 to 125 20 Ld PDIP IL IH CC at V = 5V CC Logic CD74HC273M -55 to 125 20 Ld SOIC • HCT Types Octal CD74HC273M96 -55 to 125 20 Ld SOIC - 4.5V to 5.5V Operation D- CD54HCT273F3A -55 to 125 20 Ld CERDIP - Direct LSTTL Input Logic Compatibility, Type V = 0.8V (Max), V = 2V (Min) IL IH CD74HCT273E -55 to 125 20 Ld PDIP Flip- - CMOS Input Compatibility, I ≤ 1μA at V , V l OL OH CD74HCT273M -55 to 125 20 Ld SOIC CD74HCT273M96 -55 to 125 20 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. Pinout CD54HC273, CD54HCT273 (CERDIP) CD74HC273, CD74HCT273 (PDIP, SOIC) TOP VIEW MR 1 20 V CC Q0 Q7 2 19 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
