CD74HCT194E ,High Speed CMOS Logic 4-Bit Bidirectional Universal Shift RegisterFeatures Description• Four Operating Modes The ’HC194 and CD74HCT194 are 4-bit shift registers with ..
CD74HCT194E ,High Speed CMOS Logic 4-Bit Bidirectional Universal Shift RegisterCD54HC194, CD74HC194,CD74HCT194Data sheet acquired from Harris SemiconductorSCHS164GHigh-Speed CMOS ..
CD74HCT194E ,High Speed CMOS Logic 4-Bit Bidirectional Universal Shift RegisterMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
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CD74HCT194E
High Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register
CD54HC194, CD74HC194, CD74HCT194 SCHS164G High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register September 1997 - Revised May 2006 Features Description • Four Operating Modes The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR). In the parallel mode (S0 - Shift Right, Shift Left, Hold and Reset [ /Title and S1 are high), data is loaded into the associated flip-flop • Synchronous Parallel or Serial Operation (CD74 and appears at the output after the positive transition of the • Typical f = 60MHz at V = 5V, C = 15pF, clock input (CP). During parallel loading serial data flow is MAX CC L HC194, o T = 25 C inhibited. Shift left and shift right are accomplished A CD74H synchronously on the positive clock edge with serial data • Asynchronous Master Reset CT194) entered at the shift left (DSL) serial input for the shift left mode, and at the shift right (DSR) serial input for the shift /Sub- • Fanout (Over Temperature Range) right mode. Clearing the register is accomplished by a Low - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads ject applied to the Master Reset (MR) pin. - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads (High- o o Speed • Wide Operating Temperature Range . . . -55 C to 125 C Ordering Information CMOS • Balanced Propagation Delay and Transition Times TEMP. RANGE Logic o PART NUMBER ( C) PACKAGE • Significant Power Reduction Compared to LSTTL 4-Bit Logic ICs CD54HC194F3A -55 to 125 16 Ld CERDIP • HC Types CD74HC194E -55 to 125 16 Ld PDIP - 2V to 6V Operation = 30%, N = 30% of V CD74HC194M -55 to 125 16 Ld SOIC - High Noise Immunity: N IL IH CC at V = 5V CC CD74HC194MT -55 to 125 16 Ld SOIC • HCT Types CD74HC194M96 -55 to 125 16 Ld SOIC - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, CD74HC194NSR -55 to 125 16 Ld SOP V = 0.8V (Max), V = 2V (Min) IL IH CD74HC194PW -55 to 125 16 Ld TSSOP ≤ 1µA at V , V - CMOS Input Compatibility, I l OL OH CD74HC194PWR -55 to 125 16 Ld TSSOP CD74HC194PWT -55 to 125 16 Ld TSSOP Pinout CD74HCT194E -55 to 125 16 Ld PDIP CD54HC194 (CERDIP) CD74HC194 (PDIP, SOIC, SOP, TSSOP) NOTE: When ordering, use the entire part number. The suffixes 96 CD74HCT194 (PDIP) and R denote tape and reel. The suffix T denotes a small-quantity TOP VIEW reel of 250. MR 1 16 V CC DSR 2 15 Q 0 D 3 14 Q 0 1 D 4 13 Q 1 2 D 5 12 Q 2 3 D 6 11 CP 3 DSL 7 10 S1 9 S0 GND 8 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2006, 1
