CD74HCT174M ,High Speed CMOS Logic Hex D-Type Flip-Flop with ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HCT174MG4 ,High Speed CMOS Logic Hex D-Type Flip-Flop with Reset 16-SOIC -55 to 125Featurestransition of the CLOCK input. The MR input, when low, sets• Buffered Positive Edge Trigger ..
CD74HCT175E ,High Speed CMOS Logic Quad D-Type Flip-Flop with ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HCT175M ,High Speed CMOS Logic Quad D-Type Flip-Flop with ResetLogic DiagramCCL L ONE OF FOUR F/F4 (5, 12, 13) D3( 6, 11, 14)p pDnQn nnCC LLCC LLppnnC CL LCC 2( 7 ..
CD74HCT175M ,High Speed CMOS Logic Quad D-Type Flip-Flop with ResetCD54HC175, CD74HC175,CD54HCT175, CD74HCT175Data sheet acquired from Harris SemiconductorSCHS160CHig ..
CD74HCT175M96 ,High Speed CMOS Logic Quad D-Type Flip-Flop with ResetFeaturesLSTTL devices.• Common Clock and Asynchronous Reset on FourInformation at the D input is tr ..
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CD74HCT174E-CD74HCT174M-CD74HCT174MG4
High Speed CMOS Logic Hex D-Type Flip-Flop with Reset
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 SCHS159C High-Speed CMOS Logic August 1997 - Revised October 2003 Hex D-Type Flip-Flop with Reset times is transferred to the Q output on the low to high Features transition of the CLOCK input. The MR input, when low, sets • Buffered Positive Edge Triggered Clock all outputs to a low state. • Asynchronous Common Reset [ /Title Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin (CD74 • Fanout (Over Temperature Range) compatible to the ’LS174. - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads HC174 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads , Ordering Information o o • Wide Operating Temperature Range . . . -55 C to 125 C D74 C TEMP. RANGE HCT17 • Balanced Propagation Delay and Transition Times o PART NUMBER ( C) PACKAGE 4) • Significant Power Reduction Compared to LSTTL CD54HC174F3A -55 to 125 16 Ld CERDIP Logic ICs /Sub- ject • HC Types CD54HCT174F3A -55 to 125 16 Ld CERDIP - 2V to 6V Operation (High CD74HC174E -55 to 125 16 Ld PDIP - High Noise Immunity: N = 30%, N = 30% of V IL IH CC Speed at V = 5V CC CD74HC174M -55 to 125 16 Ld SOIC CMOS • HCT Types CD74HC174MT -55 to 125 16 Ld SOIC Logic - 4.5V to 5.5V Operation Hex D- CD74HC174M96 -55 to 125 16 Ld SOIC - Direct LSTTL Input Logic Compatibility, Type V = 0.8V (Max), V = 2V (Min) IL IH CD74HCT174E -55 to 125 16 Ld PDIP - CMOS Input Compatibility, I ≤ 1µA at V , V Flip- l OL OH CD74HCT174M -55 to 125 16 Ld SOIC Flop Description CD74HCT174MT -55 to 125 16 Ld SOIC The ’HC174 and ’HCT174 are edge triggered flip-flops which CD74HCT174M96 -55 to 125 16 Ld SOIC utilize silicon gate CMOS circuitry to implement D-type flip- flops. They possess low power and speeds comparable to low NOTE: When ordering, use the entire part number. The suffix 96 power Schottky TTL circuits. The devices contain six master- denotes tape and reel. The suffix T denotes a small-quantity reel of slave flip-flops with a common clock and common reset. 250. Data on the D input having the specified setup and hold Pinout CD54HC174, CD54HCT174 (CERDIP) CD74HC174, CD74HCT174 (PDIP, SOIC) TOP VIEW MR 1 16 V CC Q 2 15 Q 0 5 D 3 14 D 0 5 D 4 13 D 1 4 Q 5 12 Q 1 4 D 6 11 D 2 3 Q 7 10 Q 2 3 GND 8 9 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
