CD74HCT125M ,High Speed CMOS Logic Quad Buffers with 3-State OutputsLogic DiagramPnA nYnnOE2CD54HC125, CD74HC125, CD54HCT125, CD74HCT125Absolute
CD74HCT125M ,High Speed CMOS Logic Quad Buffers with 3-State OutputsFeatures Description• Three-State Outputs The ’HC125 and ’HCT125 contain 4 independent three-stateb ..
CD74HCT125M ,High Speed CMOS Logic Quad Buffers with 3-State OutputsMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HCT125M96 ,High Speed CMOS Logic Quad Buffers with 3-State OutputsCD54HC125, CD74HC125,CD54HCT125, CD74HCT125Data sheet acquired from Harris SemiconductorSCHS143CHig ..
CD74HCT126E ,High Speed CMOS Logic Quad Buffers with 3-State OutputsMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HCT126M ,High Speed CMOS Logic Quad Buffers with 3-State OutputsCD54HC126, CD74HC126,CD54HCT126, CD74HCT126Data sheet acquired from Harris SemiconductorSCHS144CHig ..
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CD74HCT125E-CD74HCT125M-CD74HCT125M96
High Speed CMOS Logic Quad Buffers with 3-State Outputs
CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 SCHS143C High-Speed CMOS Logic November 1997 - Revised August 2003 Quad Buffer, Three-State Features Description • Three-State Outputs The ’HC125 and ’HCT125 contain 4 independent three-state buffers, each having its own output enable input, which when • Separate Output Enable Inputs [ /Title “HIGH” puts the output in the high impedance state. • Fanout (Over Temperature Range) (CD74 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Ordering Information HC125 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads , o o C to 125 C TEMP. RANGE • Wide Operating Temperature Range . . . -55 o D74 C PART NUMBER ( C) PACKAGE • Balanced Propagation Delay and Transition Times HCT12 CD54HC125F3A -55 to 125 14 Ld CERDIP • Significant Power Reduction Compared to LSTTL 5) Logic ICs CD54HCT125F3A -55 to 125 14 Ld CERDIP /Sub- • HC Types ject CD74HC125E -55 to 125 14 Ld PDIP - 2V to 6V Operation = 30%, N = 30% of V - High Noise Immunity: N (High IL IH CC CD74HC125M -55 to 125 14 Ld SOIC at V = 5V CC Speed CD74HC125MT -55 to 125 14 Ld SOIC • HCT Types CMOS - 4.5V to 5.5V Operation CD74HC125M96 -55 to 125 14 Ld SOIC Logic - Direct LSTTL Input Logic Compatibility, Quad V = 0.8V (Max), V = 2V (Min) CD74HCT125E -55 to 125 14 Ld PDIP IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V Buffer, l OL OH CD74HCT125M -55 to 125 14 Ld SOIC Three- CD74HCT125MT -55 to 125 14 Ld SOIC State) CD74HCT125M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC125, CD54HCT125 (CERDIP) CD74HC125, CD74HCT125 (PDIP, SOIC) TOP VIEW 1OE 1 14 V CC 1A 2 13 4OE 1Y 3 12 4A 2OE 4 11 4Y 2A 5 10 3OE 2Y 6 9 3A GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
