CD74HCT107 ,High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with ResetFeatures Description• Hysteresis on Clock Inputs for Improved Noise Immu- The ’HC107 and CD74HCT107 ..
CD74HCT107E ,High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with ResetCD54HC107, CD74HC107,CD74HCT107Data sheet acquired from Harris SemiconductorSCHS139DDual J-K Flip-F ..
CD74HCT107E ,High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HCT109E ,High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HCT109M ,High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and ResetFeatures Description• Asynchronous Set and Reset The ’HC109 and ’HCT109 are dual J-K flip-flops with ..
CD74HCT10E ,High Speed CMOS Logic Triple 3-Input NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD74HCT107-CD74HCT107E
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
CD54HC107, CD74HC107, CD74HCT107 SCHS139D Dual J-K Flip-Flop with Reset March 1998 - Revised October 2003 Negative-Edge Trigger Features Description • Hysteresis on Clock Inputs for Improved Noise Immu- The ’HC107 and CD74HCT107 utilize silicon gate CMOS nity and Increased Input Rise and Fall Times technology to achieve operating speeds equivalent to LSTTL [ /Title parts. They exhibit the low power consumption of standard • Asynchronous Reset (CD74 CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. • Complementary Outputs HC107 , These flip-flops have independent J, K, Reset and Clock • Buffered Inputs inputs and Q and Q outputs. They change state on the D74 C = 60MHz at V = 5V, C = 15pF, • Typical f MAX CC L negative-going transition of the clock pulse. Reset is o HCT10 T = 25 C A accomplished asynchronously by a low level input. 7) • Fanout (Over Temperature Range) This device is functionally identical to the HC/HCT73 but /Sub- - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads differs in terminal assignment and in some parametric limits. ject - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible (Dual o o • Wide Operating Temperature Range . . . -55 C to 125 C with the standard LS family. J-K • Balanced Propagation Delay and Transition Times Ordering Information Flip- • Significant Power Reduction Compared to LSTTL Flop TEMP. RANGE Logic ICs o with PART NUMBER ( C) PACKAGE • HC Types Reset CD54HC107F3A -55 to 125 14 Ld CERDIP - 2V to 6V Operation Nega- CD74HC107E -55 to 125 14 Ld PDIP - High Noise Immunity: N = 30%, N = 30% of V IL IH CC tive- at V = 5V CD74HC107M -55 to 125 14 Ld SOIC CC CD74HC107MT -55 to 125 14 Ld SOIC • HCT Types - 4.5V to 5.5V Operation CD74HC107M96 -55 to 125 14 Ld SOIC - Direct LSTTL Input Logic Compatibility, CD74HCT107E -55 to 125 14 Ld PDIP = 0.8V (Max), V = 2V (Min) V IL IH NOTE: When ordering, use the entire part number. The suffix 96 - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC107 (CERDIP) CD74HC107 (PDIP, SOIC) CD74HCT107 (PDIP) TOP VIEW 1J 1 14 V CC 1Q 2 13 1R 1Q 3 12 1CP 1K 4 11 2K 2Q 5 10 2R 2Q 6 9 2CP GND 7 8 2J CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
