CD74HC93M96 ,High Speed CMOS Logic 4-Bit Binary Ripple CounterCD74HC93,CD74HCT93Data sheet acquired from Harris SemiconductorSCHS138CHigh-Speed CMOS Logic4-Bit B ..
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CD74HC93E-CD74HC93M-CD74HC93M96
High Speed CMOS Logic 4-Bit Binary Ripple Counter
CD74HC93, CD74HCT93 SCHS138C High-Speed CMOS Logic 4-Bit Binary Ripple Counter August 1997 - Revised September 2003 Features Description • Can Be Configured to Divide By 2, 8, and 16 The CD74HC93 and CD74HCT93 are high-speed silicon-gate CMOS devices and are pin-compatible with low power • Asynchronous Master Reset [ /Title Schottky TTL (LSTTL). These 4-bit binary ripple counters (CD74 consist of four master-slave flip-flops internally connected to • Fanout (Over Temperature Range) provide a divide-by-two section and a divide- by-eight section. - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads HC93, Each section has a separate clock input (CP0 and CP1) to - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD74 initiate state changes of the counter on the HIGH to LOW o o • Wide Operating Temperature Range . . . -55 C to 125 C HCT93 clock transition. State changes of the Q outputs do not occur n simultaneously because of internal ripple delays. Therefore, ) • Balanced Propagation Delay and Transition Times decoded output signals are subject to decoding spikes and Sub- / • Significant Power Reduction Compared to LSTTL should not be used for clocks or strobes. ject Logic ICs A gated AND asynchronous master reset (MR1 and MR2 is (High • HC Types provided which overrides both clocks and resets (clears) all Speed - 2V to 6V Operation flip-flops. - High Noise Immunity: N = 30%, N = 30% of V CMOS IL IH CC at V = 5V Because the output from the divide by two section is not CC Logic internally connected to the succeeding stages, the device • HCT Types 4-Bit may be operated in various counting modes. - 4.5V to 5.5V Operation Binary In a 4-bit ripple counter the output Q must be connected - Direct LSTTL Input Logic Compatibility, 0 Ripple V = 0.8V (Max), V = 2V (Min) externally to input CP1. The input count pulses are applied IL IH to clock input CP0. Simultaneous frequency divisions of 2, 4, - CMOS Input Compatibility, I ≤ 1µA at V , V Counte l OL OH 8, and 16 are performed at the Q ,Q ,Q , and Q outputs 0 1 2 3 r) as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1. Pinout Simultaneous frequency divisions of 2, 4, and 8 are available CD74HC93 at the Q ,Q ,Q outputs. Independent use of the first flip- 1 2 3 (PDIP, SOIC) flop is available if the reset function coincides with the reset CD74HCT93 of the 3-bit ripple-through counter. (PDIP) TOP VIEW Ordering Information CP1 1 14 CPO TEMP. RANGE MR1 2 13 NC o PART NUMBER ( C) PACKAGE MR2 3 12 Q 0 CD74HC93E -55 to 125 14 Ld PDIP NC 4 11 Q 3 CD74HC93M -55 to 125 14 Ld SOIC V 5 10 GND CC CD74HC93MT -55 to 125 14 Ld SOIC NC 6 9 Q 1 CD74HC93M96 -55 to 125 14 Ld SOIC NC 7 8 Q 2 CD74HCT93E -55 to 125 14 Ld PDIP NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
