CD74HC73M96 ,High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with ResetFeatures Description• Hysteresis on Clock Inputs for Improved Noise The ’HC73 and CD74HCT73 utilize ..
CD74HC73M96 ,High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with ResetFeatures Description• Hysteresis on Clock Inputs for Improved Noise The ’HC73 and CD74HCT73 utilize ..
CD74HC73M96 ,High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with ResetCD54HC73, CD74HC73,CD74HCT73Data sheet acquired from Harris SemiconductorSCHS134EDual J-K Flip-Flop ..
CD74HC73M96G4 ,High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125Maximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC74E ,High Speed CMOS Logic Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC74M ,High Speed CMOS Logic Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and ResetFeatures Description• Hysteresis on Clock Inputs for Improved Noise The ’HC74 and ’HCT74 utilize si ..
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CD74HC73E-CD74HC73M-CD74HC73M96-CD74HC73M96G4
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
CD54HC73, CD74HC73, CD74HCT73 SCHS134E Dual J-K Flip-Flop with Reset February 1998 - Revised September 2003 Negative-Edge Trigger Features Description • Hysteresis on Clock Inputs for Improved Noise The ’HC73 and CD74HCT73 utilize silicon gate CMOS Immunity and Increased Input Rise and Fall Times technology to achieve operating speeds equivalent to LSTTL [ /Title parts. They exhibit the low power consumption of standard • Asynchronous Reset (CD74 CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. • Complementary Outputs HC73, CD74 These flip-flops have independent J, K, Reset and Clock • Buffered Inputs inputs and Q and Q outputs. They change state on the HCT73 = 60MHz at V = 5V, C = 15pF, • Typical f MAX CC L negative-going transition of the clock pulse. Reset is o ) T = 25 C A accomplished asynchronously by a low level input. This Sub- / device is functionally identical to the HC/HCT107 but differs • Fanout (Over Temperature Range) in terminal assignment and in some parametric limits. ject - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads (Dual - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible with the standard LS logic family. J-K o o • Wide Operating Temperature Range . . . -55 C to 125 C Flip- Ordering Information • Balanced Propagation Delay and Transition Times Flop • Significant Power Reduction Compared to LSTTL TEMP. RANGE o Logic ICs PART NUMBER ( C) PACKAGE CD54HC73F3A -55 to 125 14 Ld CERDIP • HC Types - 2V to 6V Operation CD74HC73E -55 to 125 14 Ld PDIP - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC73M -55 to 125 14 Ld SOIC at V = 5V CC CD74HC73MT -55 to 125 14 Ld SOIC • HCT Types CD74HC73M96 -55 to 125 14 Ld SOIC - 4.5V to 5.5V Operation CD74HCT73E -55 to 125 14 Ld PDIP - Direct LSTTL Input Logic Compatibility, = 0.8V (Max), V = 2V (Min) V IL IH CD74HCT73M -55 to 125 14 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC73 (CERDIP) CD74HC73, CD74HCT73 (PDIP, SOIC) TOP VIEW 1CP 1 14 1J 1R 2 13 1Q 1K 3 12 1Q V 4 11 GND CC 2CP 5 10 2K 2R 6 9 2Q 2J 7 8 2Q CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
