CD74HC7046AE ,High Speed CMOS Logic Phase-Locked Loop with VCO and Lock DetectorFeatures Description• Center Frequency of 18MHz (Typ) at V = 5V, The CD74HC7046A and CD74HCT7046A h ..
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CD74HC7046AE
High Speed CMOS Logic Phase-Locked Loop with VCO and Lock Detector
CD74HC7046A, CD74HCT7046A SCHS218C Phase-Locked Loop with VCO and Lock Detector February 1998 - Revised October 2003 Features Description • Center Frequency of 18MHz (Typ) at V = 5V, The CD74HC7046A and CD74HCT7046A high-speed CC Minimum Center Frequency of 12MHz at V silicon-gate CMOS devices, specified in compliance with CC = 4.5V [ /Title JEDEC Standard No. 7A, are phase-locked-loop (PLL) • Choice of Two Phase Comparators (CD74 circuits that contain a linear voltage-controlled oscillator - Exclusive-OR (VCO), two-phase comparators (PC1, PC2), and a lock HC704 - Edge-Triggered JK Flip-Flop detector. A signal input and a comparator input are common 6A, to each comparator. The lock detector gives a HIGH level at • Excellent VCO Frequency Linearity CD74 pin 1 (LD) when the PLL is locked. The lock detector • VCO-Inhibit Control for ON/OFF Keying and for Low capacitor must be connected between pin 15 (C ) and pin HCT70 LD Standby Power Consumption 8 (Gnd). For a frequency range of 100kHz to 10MHz, the 46A) • Minimal Frequency Drift lock detector capacitor should be 1000pF to 10pF, /Sub- respectively. • Zero Voltage Offset Due to Op-Amp Buffer ject The signal input can be directly coupled to large voltage • Operating Power-Supply Voltage Range (Phase- signals, or indirectly coupled (with a series capacitor) to - VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V Locked small voltage signals. A self-bias input circuit keeps small - Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V voltage signals within the linear region of the input amplifiers. Loop • Fanout (Over Temperature Range) With a passive low-pass filter, the 7046A forms a second- order loop PLL. The excellent VCO linearity is achieved by - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads the use of linear op-amp techniques. - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads o o • Wide Operating Temperature Range . . . -55 C to 125 C Ordering Information • Balanced Propagation Delay and Transition Times TEMP. RANGE o • Significant Power Reduction Compared to LSTTL PART NUMBER ( C) PACKAGE Logic ICs CD74HC7046AE -55 to 125 16 Ld PDIP • HC Types CD74HC7046AM -55 to 125 16 Ld SOIC - 2V to 6V Operation CD74HC7046AMT -55 to 125 16 Ld SOIC - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC7046AM96 -55 to 125 16 Ld SOIC at V = 5V CC CD74HCT7046AE -55 to 125 16 Ld PDIP • HCT Types - 4.5V to 5.5V Operation CD74HCT7046AM -55 to 125 16 Ld SOIC - Direct LSTTL Input Logic Compatibility, CD74HCT7046AMT -55 to 125 16 Ld SOIC V = 0.8V (Max), V = 2V (Min) IL IH CD74HCT7046AM96 -55 to 125 16 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel Applications of 250. • FM Modulation and Demodulation • Frequency Synthesis and Multiplication • Frequency Discrimination • Tone Decoding • Data Synchronization and Conditioning • Voltage-to-Frequency Conversion • Motor-Speed Control • Related Literature - AN8823, CMOS Phase-Locked-Loop Application Using the CD74HC/HCT7046A and CD74HC/HCT7046A 0.1 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
