CD74HC640E ,High Speed CMOS Logic Octal Inverting Bus Transceivers with 3-State OutputsMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC640M ,High Speed CMOS Logic Octal Inverting Bus Transceivers with 3-State OutputsFeatures Description• Buffered Inputs The ’HC640 and ’HCT640 silicon-gate CMOS three-statebidirecti ..
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CD74HC688E ,High Speed CMOS Logic 8-Bit Magnitude ComparatorLogic DiagramA0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B72 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 ..
CL10C101JBNC , Multilayer Ceramic Capacitor
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CD74HC640E-CD74HC640M
High Speed CMOS Logic Octal Inverting Bus Transceivers with 3-State Outputs
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 SCHS192B High-Speed CMOS Logic January 1998 - Revised May 2003 Octal Three-State Bus Transceiver, Inverting Features Description • Buffered Inputs The ’HC640 and ’HCT640 silicon-gate CMOS three-state bidirectional inverting and non-inverting buffers are intended • Three-State Outputs [ /Title for two-way asynchronous communication between data buses. They have high drive current outputs which enable (CD74 • Applications in Multiple-Data-Bus Architecture high-speed operation when driving large bus capacitances. HC640 • Fanout (Over Temperature Range) These circuits possess the low power dissipation of CMOS , - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads circuits, and have speeds comparable to low power Schottky CD74 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TTL circuits. They can drive 15 LSTTL loads. The ’HC640 and ’HCT640 are inverting buffers. HCT64 o o • Wide Operating Temperature Range . . . -55 C to 125 C 0) The direction of data flow (A to B, B to A) is controlled by the • Balanced Propagation Delay and Transition Times DIR input. /Sub- • Significant Power Reduction Compared to LSTTL ject Outputs are enabled by a low on the Output Enable input Logic ICs (OE); a high OE puts these devices in the high impedance (High mode. • HC Types Speed - 2V to 6V Operation CMOS Ordering Information - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CC TEMP. RANGE o PART NUMBER ( C) PACKAGE • HCT Types - 4.5V to 5.5V Operation CD54HC640F3A -55 to 125 20 Ld CERDIP - Direct LSTTL Input Logic Compatibility, CD54HCT640F3A -55 to 125 20 Ld CERDIP V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1μA at V , V l OL OH CD74HC640E -55 to 125 20 Ld PDIP CD74HC640M -55 to 125 20 Ld SOIC Pinout CD74HCT640E -55 to 125 20 Ld PDIP CD54HC640, CD54HCT640 CD74HCT640M -55 to 125 20 Ld SOIC (CERDIP) CD74HC640, CD74HCT640 (PDIP, SOIC) TOP VIEW DIR 1 20 V CC A0 2 19 OE A1 B0 3 18 A2 4 17 B1 A3 5 16 B2 A4 B3 6 15 A5 B4 7 14 8 13 B5 A6 9 12 A7 B6 GND 10 11 B7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
