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CD74HC595E-CD74HC595EE4-CD74HC595M-CD74HC595M96-CD74HC595NSR Fast Delivery,Good Price
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CD74HC595ETIN/a1000avai8-Bit Shift Registers With 3-State Output Registers
CD74HC595EE4TIN/a1000avai8-Bit Shift Registers With 3-State Output Registers 16-PDIP -55 to 125
CD74HC595MTIN/a1000avai8-Bit Shift Registers With 3-State Output Registers
CD74HC595M96TIN/a1000avai8-Bit Shift Registers With 3-State Output Registers
CD74HC595NSRTIN/a7avai8-Bit Shift Registers With 3-State Output Registers
CD74HC595SM96TIN/a11avai8-Bit Shift Registers With 3-State Output Registers


CD74HC595E ,8-Bit Shift Registers With 3-State Output Registers/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
CD74HC595EE4 ,8-Bit Shift Registers With 3-State Output Registers 16-PDIP -55 to 125            SCHS353 − JANUARY 2004DW, E, M, NS, OR SM PACK ..
CD74HC595M ,8-Bit Shift Registers With 3-State Output Registers            SCHS353 − JANUARY 2004DW, E, M, NS, OR SM PACK ..
CD74HC595M96 ,8-Bit Shift Registers With 3-State Output Registers            SCHS353 − JANUARY 2004DW, E, M, NS, OR SM PACK ..
CD74HC595NSR ,8-Bit Shift Registers With 3-State Output Registers/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
CD74HC595SM96 ,8-Bit Shift Registers With 3-State Output Registers/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
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CD74HC595E-CD74HC595EE4-CD74HC595M-CD74HC595M96-CD74HC595NSR-CD74HC595SM96
8-Bit Shift Registers With 3-State Output Registers
Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Shift Register Has Direct Cleardescription/ordering information
The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and
storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial
output for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
ORDERING INFORMATION
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.E
GND
RCLK
SRCLK
SRCLR
QH′
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