CD74HC564M96 ,High Speed CMOS Logic Octal Positive-Edge-Triggered Inverting D-Type Flip-Flops with 3-State OutputsMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC573E ,High Speed CMOS Logic Octal Transparent Latches with 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD74HC573M ,High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs CD54HC573, CD74HC573 OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCLS454A – FEBRUARY 2001 ..
CD74HC573M ,High Speed CMOS Logic Octal Transparent Latches with 3-State Outputslogic diagram (positive logic)1OE11LEC1191Q21D1DTo Seven Other Channels†absolute
CD74HC573M96G4 ,High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs 20-SOIC -55 to 125 CD54HC573, CD74HC573 OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCLS454A – FEBRUARY 2001 ..
CD74HC573MG4 ,High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs 20-SOIC -55 to 125maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
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CD74HC564E-CD74HC564M-CD74HC564M96
High Speed CMOS Logic Octal Positive-Edge-Triggered Inverting D-Type Flip-Flops with 3-State Outputs
CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564 SCHS188C High-Speed CMOS Logic Octal D-Type Flip-Flop, January 1998 - Revised April 2004 Three-State Inverting Positive-Edge Triggered Features Description • Buffered Inputs The ’HC534, ’HCT534, ’HC564, and ’HCT564 are high speed Octal D-Type Flip-Flops manufactured with silicon gate CMOS • Common Three-State Output-Enable Control [ /Title technology. They possess the low power consumption of stan- (CD74 dard CMOS integrated circuits, as well as the ability to drive • Three-State Outputs 15 LSTTL loads. Due to the large output drive capability and HC534 • Bus Line Driving Capability the three-state feature, these devices are ideally suited for , interfacing with bus lines in a bus organized system. The two = 5V, • Typical Propagation Delay = 13ns at V CC D74 C o types are functionally identical and differ only in their pinout C = 15pF, T = 25 C (Clock to Output) L A arrangements. HCT53 • Fanout (Over Temperature Range) 4, The ’HC534, ’HCT534, ’HC564, and ’HCT564 are positive - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads edge triggered flip-flops. Data at the D inputs, meeting the CD74 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads setup and hold time requirements, are inverted and trans- HC564 o o ferred to the Q outputs on the positive going transition of the • Wide Operating Temperature Range . . . -55 C to 125 C , CLOCK input. When a high logic level is applied to the OUT- • Balanced Propagation Delay and Transition Times PUT ENABLE input, all outputs go to a high impedance state, D74 C regardless of what signals are present at the other inputs and HCT56 • Significant Power Reduction Compared to LSTTL the state of the storage elements. Logic ICs The HCT logic family is speed, function, and pin compatible • HC Types with the standard LS logic family. - 2V to 6V Operation Ordering Information - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V TEMP. RANGE CC o PART NUMBER ( C) PACKAGE • HCT Types CD54HC534F3A -55 to 125 20 Ld CERDIP - 4.5V to 5.5V Operation CD54HC564F3A -55 to 125 20 Ld CERDIP - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) CD54HCT534F3A -55 to 125 20 Ld CERDIP IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V CD54HCT564F3A -55 to 125 20 Ld CERDIP l OL OH CD74HC534E -55 to 125 20 Ld PDIP CD74HC564E -55 to 125 20 Ld PDIP CD74HC564M -55 to 125 20 Ld SOIC CD74HC564M96 -55 to 125 20 Ld SOIC CD74HCT534E -55 to 125 20 Ld PDIP CD74HCT564E -55 to 125 20 Ld PDIP CD74HCT564M -55 to 125 20 Ld SOIC CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, 1
