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CD74HC541E不知厂家N/a8avaiHigh Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State Outputs
CD74HC541MHARRISN/a64avaiHigh Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State Outputs
CD74HC541MTIN/a22avaiHigh Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State Outputs


CD74HC541M ,High Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State OutputsFeatures Description• ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting The ’HC540 ..
CD74HC541M ,High Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State OutputsMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC563E ,High Speed CMOS Logic Octal Inverting Transparent Latches with 3-State OutputsFeatures Description• Common Latch-Enable Control The ’HC533, ’HCT533, ’HC563, and CD74HCT563 arehi ..
CD74HC564E ,High Speed CMOS Logic Octal Positive-Edge-Triggered Inverting D-Type Flip-Flops with 3-State OutputsFeatures Description• Buffered Inputs The ’HC534, ’HCT534, ’HC564, and ’HCT564 are high speedOctal ..
CD74HC564M ,High Speed CMOS Logic Octal Positive-Edge-Triggered Inverting D-Type Flip-Flops with 3-State OutputsFeatures Description• Buffered Inputs The ’HC534, ’HCT534, ’HC564, and ’HCT564 are high speedOctal ..
CD74HC564M96 ,High Speed CMOS Logic Octal Positive-Edge-Triggered Inverting D-Type Flip-Flops with 3-State OutputsMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD74HC541E-CD74HC541M
High Speed CMOS Logic Octal Non-Inverting Buffers and Line Drivers with 3-State Outputs
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 SCHS189C High-Speed CMOS Logic January 1998 - Revised July 2004 Octal Buffer and Line Drivers, Three-State Features Description • ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting The ’HC540 and CD74HCT540 are Inverting Octal Buffers and Line Drivers with Three-State Outputs and the capability • ’HC541, ’HCT541 . . . . . . . . . . . . . . . . . . . . . . Non-Inverting [ /Title to drive 15 LSTTL loads. The ’HC541 and ’HCT541 are Non- (CD74 Inverting Octal Buffers and Line Drivers with Three-State Out- • Buffered Inputs puts that can drive 15 LSTTL loads. The Output Enables HC540 • Three-State Outputs (OE1) and (OE2) control the Three-State Outputs. If either , OE1 or OE2 is HIGH the outputs will be in the high imped- • Bus Line Driving Capability D74 C ance state. For data output OE1 and OE2 both must be LOW. = 5V, • Typical Propagation Delay = 9ns at V CC HCT54 o Ordering Information C = 15pF, T = 25 C L A 0, TEMP. RANGE • Fanout (Over Temperature Range) CD74 o PART NUMBER ( C) PACKAGE - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads HC541 CD54HC540F3A -55 to 125 20 Ld CERDIP - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads , CD54HC541F3A -55 to 125 20 Ld CERDIP o o • Wide Operating Temperature Range . . . -55 C to 125 C D74 C CD54HCT541F3A -55 to 125 20 Ld CERDIP HCT54 • Balanced Propagation Delay and Transition Times CD74HC540E -55 to 125 20 Ld PDIP • Significant Power Reduction Compared to LSTTL CD74HC540M -55 to 125 20 Ld SOIC Logic ICs CD74HC540M96 -55 to 125 20 Ld SOIC • HC Types CD74HC541E -55 to 125 20 Ld PDIP - 2V to 6V Operation CD74HC541M -55 to 125 20 Ld SOIC - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC541M96 -55 to 125 20 Ld SOIC at V = 5V CC CD74HC541PW -55 to 125 20 Ld TSSOP • HCT Types CD74HC541PWR -55 to 125 20 Ld TSSOP - 4.5V to 5.5V Operation CD74HCT540E -55 to 125 20 Ld PDIP - Direct LSTTL Input Logic Compatibility, CD74HCT540M -55 to 125 20 Ld SOIC V = 0.8V (Max), V = 2V (Min) IL IH CD74HCT540M96 -55 to 125 20 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HCT541E -55 to 125 20 Ld PDIP CD74HCT541M -55 to 125 20 Ld SOIC CD74HCT541M96 -55 to 125 20 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, 1
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