CD74HC4538NSR ,High Speed CMOS Logic Dual Retriggerable Precision Monostable MultivibratorsLOGIC DIAGRAM (1 MONO)FUNCTIONAL TERMINAL CONNECTIONSV TO GND TO INPUT PULSE TO OTHERCCTERMINAL NUM ..
CD74HC4538PW ,High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrators CD54HC4538, CD74HC4538,CD54HCT4538, CD74HCT4538Data sheet acquired from Harris SemiconductorSCHS12 ..
CD74HC4538PWG4 ,High-Speed CMOS Logic Dual Retriggerable Precision Monostable MultivibratorMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD74HC4538PWR ,High Speed CMOS Logic Dual Retriggerable Precision Monostable MultivibratorsMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD74HC4538PWR ,High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrators CD54HC4538, CD74HC4538,CD54HCT4538, CD74HCT4538Data sheet acquired from Harris SemiconductorSCHS12 ..
CD74HC4538QM96Q1 ,High Speed CMOS Logic Dual Retriggerable Precision Monostable MultivibratorsCD74HC4538-Q1HIGH-SPEED CMOS LOGIC DUAL RETRIGGERABLEPRECISION MONOSTABLE MULTIVIBRATORSCLS595A − N ..
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CD74HC4538E-CD74HC4538M-CD74HC4538M96-CD74HC4538NSR-CD74HC4538PW-CD74HC4538PWG4-CD74HC4538PWR
High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrators
CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 SCHS123E High-Speed CMOS Logic Dual Retriggerable June 1998 - Revised October 2003 Precision Monostable Multivibrator Features Description • Retriggerable/Resettable Capability The ’HC4538 and ’HCT4538 are dual retriggerable/resettable monostable precision multivibrators • Trigger and Reset Propagation Delays Independent of for fixed voltage timing applications. An external resistor [ /Title R , C X X (R ) and an external capacitor (C ) control the timing and X X (CD54 the accuracy for the circuit. Adjustment of R and C • Triggering from the Leading or Trailing Edge X X HC453 provides a wide range of output pulse widths from the Q and Q Buffered Outputs Available • Q and Q terminals. The propagation delay from trigger input-to- 8, output transition and the propagation delay from reset input- • Separate Resets CD74 to-output transition are independent of R and C . X X HC453 • Wide Range of Output Pulse Widths B) Leading-edge triggering (A) and trailing edge triggering ( 8, B Inputs • Schmitt Trigger Input on A and inputs are provided for triggering from either edge of the CD74 input pulse. An unused “A” input should be tied to GND and • Retrigger Time is Independent of C X HCT45 an unused B should be tied to V . On power up the IC is CC • Fanout (Over Temperature Range) reset. Unused resets and sections must be terminated. In 38) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads normal operation the circuit retriggers on the application of /Sub- each new trigger pulse. To operate in the non-triggerable - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads ject mode Q is connected to B when leading edge triggering (A) o o • Wide Operating Temperature Range . . . -55 C to 125 C (High is used or Q is connected to A when trailing edge triggering (B) is used. The period (τ) can be calculated from τ = (0.7) Speed • Balanced Propagation Delay and Transition Times R , C ; R is 5kΩ. C is 0pF. X X MIN MIN CMOS • Significant Power Reduction Compared to LSTTL Logic Logic ICs Ordering Information • HC Types TEMP. RANGE - 2V to 6V Operation o PART NUMBER ( C) PACKAGE - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD54HC4538F3A -55 to 125 16 Ld CERDIP at V = 5V CC CD54HCT4538F3A -55 to 125 16 Ld CERDIP • HCT Types - 4.5V to 5.5V Operation CD74HC4538E -55 to 125 16 Ld PDIP - Direct LSTTL Input Logic Compatibility, CD74HC4538M -55 to 125 16 Ld SOIC V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HC4538MT -55 to 125 16 Ld SOIC CD74HC4538M96 -55 to 125 16 Ld SOIC Pinout CD54HC4538, CD54HCT4538 CD74HC4538NSR -55 to 125 16 Ld SOP (CERDIP) CD74HC4538PW -55 to 125 16 Ld TSSOP CD74HC4538 (PDIP, SOIC, SOP, TSSOP) CD74HC4538PWR -55 to 125 16 Ld TSSOP CD74HCT4538 (PDIP, SOIC) CD74HC4538PWT -55 to 125 16 Ld TSSOP TOP VIEW CD74HCT4538E -55 to 125 16 Ld PDIP 1C 1 16 V X CC CD74HCT4538M -55 to 125 16 Ld SOIC 1R C 2 15 2C X X X 1R 3 14 2R C X X CD74HCT4538MT -55 to 125 16 Ld SOIC 1A 4 13 2R CD74HCT4538M96 -55 to 125 16 Ld SOIC 1B 5 12 2A 1Q 6 11 2B NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity 1Q 7 10 2Q reel of 250. GND 8 9 2Q CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
