CD74HC42E ,High Speed CMOS Logic 1-of-10 BCD to Decimal DecoderMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC42E ,High Speed CMOS Logic 1-of-10 BCD to Decimal DecoderFeatures Description• Buffered Inputs and Outputs The ’HC42 and CD74HCT42 BCD-to-Decimal Decodersut ..
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CD74HC4316M ,High Speed CMOS Quad Analog Switches with Level TranslationLogic DiagramnYTO 3 OTHERVSWITCHES CCVCCLOGICLEVEL nZECONV.VEEVnS EEFIGURE 1. ONE SWITCH2CD54HC4316 ..
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CD74HC42E
High Speed CMOS Logic 1-of-10 BCD to Decimal Decoder
CD54HC42, CD74HC42, CD74HCT42 SCHS133C High-Speed CMOS Logic August 1997 - Revised May 2003 BCD-to-Decimal Decoders (1 of 10) Features Description • Buffered Inputs and Outputs The ’HC42 and CD74HCT42 BCD-to-Decimal Decoders utilize silicon-gate CMOS technology to achieve operating = 5V, • Typical Propagation Delay: 12ns at V [ /Title CC speeds similar to LSTTL decoders with the low power o C = 15pF, T = 25 C L A consumption of standard CMOS integrated circuits. These (CD74H devices have the capability of driving 10 LSTLL loads and • Fanout (Over Temperature Range) C42, are compatible with the standard LS logic family. One of ten - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads CD74H outputs (low on select) is selected in accordance with the - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CT42) BCD input. Non-valid BCD inputs result in none of the o o • Wide Operating Temperature Range . . . -55 C to 125 C outputs being selected (all outputs are high). /Subject (High • Balanced Propagation Delay and Transition Times Ordering Information Speed • Significant Power Reduction Compared to LSTTL o CMOS Logic ICs PART NUMBER TEMP. RANGE ( C) PACKAGE Logic • HC Types CD54HC42F3A -55 to 125 16 Ld CERDIP BCD To - 2V to 6V Operation CD74HC42E -55 to 125 16 Ld PDIP Deci- - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CD74HC42M -55 to 125 16 Ld SOIC CC • HCT Types CD74HCT42E -55 to 125 16 Ld PDIP - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1μA at V , V l OL OH Pinout CD54HC42 (CERDIP) CD74HC42 (PDIP, SOIC) CD74HCT42 (PDIP) TOP VIEW Y0 1 16 V CC Y1 2 15 A0 Y2 3 14 A1 Y3 4 13 A2 Y4 5 12 A3 Y5 6 11 Y9 Y6 7 10 Y8 GND 8 9 Y7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003 . 1
