CD74HC4094NSR ,High Speed CMOS Logic 8-Stage Shift-and-Store Bus Register with 3-Stage OutputsCD54HC4094, CD74HC4094,CD74HCT4094Data sheet acquired from Harris SemiconductorSCHS211EHigh−Speed C ..
CD74HC4094PWRG4 ,High Speed CMOS Logic 8-Stage Shift-and-Store Bus Register with 3-Stage Outputs 16-TSSOP -55 to 125Maximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
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CD74HC4094E-CD74HC4094M-CD74HC4094M96-CD74HC4094NSR-CD74HC4094PWRG4
High Speed CMOS Logic 8-Stage Shift-and-Store Bus Register with 3-Stage Outputs
CD54HC4094, CD74HC4094, CD74HCT4094 SCHS211E High−Speed CMOS Logic November 1997 − Revised December 2010 8−Stage Shift and Store Bus Register, Three−State Two serial outputs are available for cascading a number of Features these devices. Data is available at the QS serial output 1 ¥ Buffered Inputs terminal on positive clock edges to allow for high−speed ¥ Separate Serial Outputs Synchronous to Both operation in cascaded system in which the clock rise time is [ /Title Positive and Negative Clock Edges For Cascading fast. The same serial information, available at the QS 2 (CD74H terminal on the next negative clock edge, provides a means ¥ Fanout (Over Temperature Range) C4094, for cascading these devices when the clock rise time is slow. − Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads CD74H − Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information o o CT4094 ¥ Wide Operating T emperature Rang e . . .−55 C to 125 C ) TEMP. RANGE ¥ Balanced Propagation Delay and Transition Times o PART NUMBER ( C) PACKAGE /Sub− ¥ Signi cant Power Reduction Compared to LSTTL ject Logic ICs CD54HC4094F3A −55 to 125 16 Ld CERDIP (High ¥ HC Types CD74HC4094E −55 to 125 16 Ld PDIP Speed − 2V to 6V Operation CD74HC4094M −55 to 125 16 Ld SOIC CMOS − High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CD74HC4094MT −55 to 125 16 Ld SOIC Logic 8− CC ¥ HCT Types CD74HC4094M96G3 −55 to 125 16 Ld SOIC − 4.5V to 5.5V Operation CD74HC4094NSR −55 to 125 16 Ld SOP − Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) IL IH CD74HC4094PW −55 to 125 16 Ld TSSOP − CMOS Input Compatibility, I ≤ 1μA at V , V l OL OH CD74HC4094PWR −55 to 125 16 Ld TSSOP Description CD74HC4094PWT −55 to 125 16 Ld TSSOP The ÕHC4094and CD74HCT4094 are 8−stage serial shift registers having a storage latch associated with each stage CD74HCT4094E −55 to 125 16 Ld PDIP for strobing data from the serial input to parallel buffered CD74HCT4094M −55 to 125 16 Ld SOIC three−stateoutputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive CD74HCT4094MT −55 to 125 16 Ld SOIC clock transitions. The data in each shift register stage is CD74HCT4094M96 −55 to 125 16 Ld SOIC transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs NOTE: When ordering, use the entire part number. The suf xes 96 whenever the Output−Enable signal is high. and R denote tape and reel. The suf x T denotes a small−quantity reel of 250. Pinout CD54HC4094 (CERDIP) CD74HC4094 (PDIP, SOIC, SOP, TSSOP) CD74HCT4094 (PDIP, SOIC) TOP VIEW STROBE 1 16 V CC DATA 2 15 OE CP 3 14 Q 4 Q 4 13 Q 0 5 Q 5 12 Q 1 6 Q 6 11 Q 2 7 Q 7 10 QS 2 3 GND 8 9 QS 1 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2003, − 1 −
