CD74HC4060M96 ,High Speed CMOS Logic 14-Stage Binary Counter with OscillatorMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC4060MG4 ,High Speed CMOS Logic 14-Stage Binary Counter with Oscillator 16-SOIC -55 to 125CD54HC4060, CD74HC4060,CD54HCT4060, CD74HCT4060Data sheet acquired from Harris SemiconductorSCHS207 ..
CD74HC4060PWR ,High Speed CMOS Logic 14-Stage Binary Counter with OscillatorCD54HC4060, CD74HC4060,CD54HCT4060, CD74HCT4060Data sheet acquired from Harris SemiconductorSCHS207 ..
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CD74HC4066M ,High Speed CMOS Logic Quad Bilateral SwitchesMaximum Ratings” may cause permanent damage to the device. This is a stress only rating and operati ..
CL ,Wirewound Resistors, Commercial Power, Tab Type Terminals, Variety of core diameters and lengths, Numerous mounting hole sizes and shapes, High performance for low cost , contact ww2aresistors Document Number 3022244 Revision 04-Sep-02CLWirewound Resistors, Commercia ..
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CD74HC4060E-CD74HC4060M96-CD74HC4060MG4-CD74HC4060PWR
High Speed CMOS Logic 14-Stage Binary Counter with Oscillator
CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 SCHS207G High-Speed CMOS Logic February 1998 - Revised October 2003 14-Stage Binary Counter with Oscillator the negative transition of φI (and φO). All inputs and outputs Features are buffered. Schmitt trigger action on the input-pulse-line • Onboard Oscillator permits unlimited rise and fall times. • Common Reset [ /Title In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same (CD74 • Negative-Edge Clocking as in the HC4060; only the MR input in the HCT4060 has HC406 • Fanout (Over Temperature Range) TTL switching levels. 0, - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads CD74 Ordering Information - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads HCT40 o o • Wide Operating Temperature Range . . . -55 C to 125 C TEMP. RANGE 60) o PART NUMBER ( C) PACKAGE • Balanced Propagation Delay and Transition Times /Sub- CD54HC4060F3A -55 to 125 16 Ld CERDIP • Significant Power Reduction Compared to LSTTL ject Logic ICs CD54HCT4060F3A -55 to 125 16 Ld CERDIP (High • HC Types Speed CD74HC4060E -55 to 125 16 Ld PDIP - 2V to 6V Operation CMOS CD74HC4060M -55 to 125 16 Ld SOIC - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CC CD74HC4060MT -55 to 125 16 Ld SOIC • HCT Types CD74HC4060M96 -55 to 125 16 Ld SOIC - 4.5V to 5.5V Operation CD74HC4060PW -55 to 125 16 Ld TSSOP - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) IL IH CD74HC4060PWR -55 to 125 16 Ld TSSOP - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HC4060PWT -55 to 125 16 Ld TSSOP Description CD74HCT4060E -55 to 125 16 Ld PDIP The ’HC4060 and ’HCT4060 each consist of an oscillator CD74HCT4060M -55 to 125 16 Ld SOIC section and 14 ripple-carry binary counter stages. The CD74HCT4060MT -55 to 125 16 Ld SOIC oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which CD74HCT4060M96 -55 to 125 16 Ld SOIC resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset NOTE: When ordering, use the entire part number. The suffixes 96 function. All counter stages are master-slave flip-flops. The and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. state of the counter is advanced one step in binary order on Pinout CD54HC4060, CD54HCT4060 (CERDIP) CD74HC4060 (PDIP, SOIC, TSSOP) CD74HCT4060 (PDIP, SOIC) TOP VIEW 16 V Q12 1 CC Q13 2 15 Q10 Q14 3 14 Q8 Q6 4 13 Q9 Q5 5 12 MR Q7 6 11 φI Q4 7 10 φO GND 8 9 φO CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
