CD74HC4059M96 ,High Speed CMOS Logic CMOS Programmable Divide-by-N CounterMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD74HC4060M96 ,High Speed CMOS Logic 14-Stage Binary Counter with OscillatorMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC4060MG4 ,High Speed CMOS Logic 14-Stage Binary Counter with Oscillator 16-SOIC -55 to 125CD54HC4060, CD74HC4060,CD54HCT4060, CD74HCT4060Data sheet acquired from Harris SemiconductorSCHS207 ..
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CL ,Wirewound Resistors, Commercial Power, Tab Type Terminals, Variety of core diameters and lengths, Numerous mounting hole sizes and shapes, High performance for low cost , contact ww2aresistors Document Number 3022244 Revision 04-Sep-02CLWirewound Resistors, Commercia ..
CL10C101JBNC , Multilayer Ceramic Capacitor
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CD74HC4059M96
High Speed CMOS Logic CMOS Programmable Divide-by-N Counter
CD54HC4059, CD74HC4059 SCHS206B High-Speed CMOS Logic February 1998 - Revised May 2003 CMOS Programmable Divide-by-N Counter Features Description • Synchronous Programmable ÷N Counter N = 3 to 9999 The ’HC4059 are high-speed silicon-gate devices that are or 15999 pin-compatible with the CD4059A devices of the CD4000B [ /Title series. These devices are divide-by-N down-counters that • Presettable Down-Counter can be programmed to divide an input frequency by any (CD74 number “N” from 3 to 15,999. The output signal is a pulse • Fully Static Operation HC4059 one clock cycle wide occurring at a rate equal to the input ) • Mode-Select Control of Initial Decade Counting frequency divide by N. The down-counter is preset by means Function (÷10, 8, 5, 4, 2) /Sub- of 16 jam inputs. ject • Master Preset Initialization The three Mode-Select Inputs K ,K and K determine the a b c (High- modulus (“divide-by” number) of the first and last counting • Latchable ÷N Output sections in accordance with the truth table. Every time the first Speed • Fanout (Over Temperature Range) (fastest) counting section goes through one cycle, it reduces by CMOS - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads 1 the number that has been preset (jammed) into the three Logic decades of the intermediate counting section an the last - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CMOS counting section, which consists of flip-flops that are not o o • Wide Operating Temperature Range . . . -55 C to 125 C needed for opening the first counting section. For example, in Pro- the ÷2 mode, only one flip-flop is needed in the first counting • Balanced Propagation Delay and Transition Times section. Therefore the last counting section has three flip-flops • Significant Power Reduction Compared to LSTTL that can be preset to a maximum count of seven with a place Logic ICs value of thousands. If ÷10 is desired for the first section, K is a set “high”, K “high” and K “low”. Jam inputs J1, J2, J3, and J4 b c • HC Types are used to preset the first counting section and there is no last - 2V to 6V Operation counting section. The intermediate counting section consists of = 30%, N = 30% of V - High Noise Immunity: N IL IH CC three cascaded BCD decade (÷10) counters presettable by at V = 5V CC means of Jam Inputs J5 through J16. The Mode-Select Inputs permit frequency-synthesizer Applications channel separations of 10, 12.5, 20, 25 or 50 parts. These • Communications Digital Frequency Synthesizers; inputs set the maximum value of N at 9999 (when the first VHF, UHF, FM, AM, etc. counting section divides by 5 or 10) or 15,999 (when the first counting section divides by 8, 4, or 2). • Fixed or Programmable Frequency Division The three decades of the intermediate counter can be preset • “Time Out” Timer for Consumer-Application Industrial to a binary 15 instead of a binary 9, while their place values Controls are still 1, 10, and 100, multiplied by the number of the ÷N mode. For example, in the ÷8 mode, the number from which Ordering Information counting down begins can be preset to: 3rd Decade 1500 TEMP. RANGE o 2nd Decade 150 PART NUMBER ( C) PACKAGE 1st Decade 15 CD54HC4059F3A -55 to 125 24 Ld CERDIP Last Counting Section 1000 CD74HC4059E -55 to 125 24 Ld PDIP The total of these numbers (2665) times 8 equals 12,320. CD74HC4059M96 -55 to 125 24 Ld SOIC The first counting section can be preset to 7. Therefore, 21,327 is the maximum possible count in the ÷8 mode. NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The highest count of the various modes is shown in the Extended Counter Range column. Control inputs K and K b c can be used to initiate and lock the counter in the “master preset” state. In this condition the flip-flops in the counter are preset in accordance with the jam inputs and the counter remains in that state as long as K and K both remain low. The b c counter begins to count down from the preset state when a counting mode other than the master preset mode is selected. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
