CD74HC4049PWR ,High Speed CMOS Logic Hex Inverting BuffersCD54HC4049, CD74HC4049,CD54HC4050, CD74HC4050Data sheet acquired from Harris SemiconductorSCHS205IH ..
CD74HC4050 ,High Speed CMOS Logic Hex Non-Inverting BuffersMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD74HC4050E ,High Speed CMOS Logic Hex Non-Inverting BuffersFeatures Description• Typical Propagation Delay: 6ns at V = 5V,CCThe ’HC4049 and ’HC4050 are fabric ..
CD74HC4050M ,High Speed CMOS Logic Hex Non-Inverting BuffersLogic DiagramsHC4049 HC4050AYA Y2CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050Absolute
CD74HC4050M96 ,High Speed CMOS Logic Hex Non-Inverting BuffersMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD74HC4050NSR ,High Speed CMOS Logic Hex Non-Inverting BuffersFeatures Description• Typical Propagation Delay: 6ns at V = 5V,CCThe ’HC4049 and ’HC4050 are fabric ..
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CD74HC4049E-CD74HC4049PWR
High Speed CMOS Logic Hex Inverting Buffers
CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 SCHS205I High-Speed CMOS Logic February 1998 - Revised February 2005 Hex Buffers, Inverting and Non-Inverting Features Description • Typical Propagation Delay: 6ns at V = 5V, CC The ’HC4049 and ’HC4050 are fabricated with high-speed o C = 15pF, T = 25 C L A silicon gate technology. They have a modified input [ /Title protection structure that enables these parts to be usedas = 16V • High-to-Low Voltage Level Converter for up to V l (CD74H logic level translators which convert high-level logic to a low- • Fanout (Over Temperature Range) C4049, level logic while operating off the low-level logic supply. For - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads example, 15-V input pulse levels can be down-converted to CD74H - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads 0-V to 5-V logic levels. The modified input protection C4050) structure protects the input from negative electrostatic o o • Wide Operating Temperature Range . . .–55 C to 125 C /Sub- discharge. These parts also can be used as simple buffers ject or inverters without level translation. The ’HC4049 and • Balanced Propagation Delay and Transition Times ’HC4050 are enhanced versions of equivalent CMOS types. (High • Significant Power Reduction Compared to LSTTL Speed Logic ICs Ordering Information CMOS • HC Types Logic TEMP. RANGE - 2V to 6V Operation o PART NUMBER ( C) PACKAGE Hex - High Noise Immunity: N = 30%, N = 30%of V at IL IH CC V = 5V CD54HC4049F3A –55 to 125 16 Ld CERDIP CC CD54HC4050F3A –55 to 125 16 Ld CERDIP Pinout CD74HC4049E –55 to 125 16 Ld PDIP CD54HC4049, CD54HC4050 CD74HC4049M –55 to 125 16 Ld SOIC (CERDIP) CD74HCT4050MT –55 to 125 16 Ld SOIC CD74HC4049, CD74HC4050 (PDIP, SOIC, SOP, TSSOP) CD74HC4049M96 –55 to 125 16 Ld SOIC TOP VIEW 4049 4050 4050 4049 CD74HC4049NSR –55 to 125 16 Ld SOP 16 NC NC V V 1 CC CC CD74HC4049PW –55 to 125 16 Ld TSSOP 15 6Y 6Y 1Y 1Y 2 CD74HC4049PWR –55 to 125 16 Ld TSSOP 1A 1A 3 14 6A 6A 2Y 2Y 4 13 NC NC CD74HC4049PWT –55 to 125 16 Ld TSSOP 2A 2A 5 12 5Y 5Y CD74HC4050E –55 to 125 16 Ld PDIP 3Y 3Y 6 11 5A 5A CD74HC4050M –55 to 125 16 Ld SOIC 3A 3A 7 10 4Y 4Y CD74HC4050MT –55 to 125 16 Ld SOIC GND GND 8 9 4A 4A CD74HC4050M96 –55 to 125 16 Ld SOIC CD74HC4050NSR –55 to 125 16 Ld SOP CD74HC4050PW –55 to 125 16 Ld TSSOP CD74HC4050PWR –55 to 125 16 Ld TSSOP CD74HC4050PWT –55 to 125 16 Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2005, 1
