CD74HC4024PWR ,High Speed CMOS Logic 7-Stage Binary Ripple CounterCD54HC4024, CD74HC4024,CD54HCT4024, CD74HCT4024Data sheet acquired from Harris SemiconductorSCHS202 ..
CD74HC4040 ,High Speed CMOS Logic 12-Stage Binary CounterLogic Diagram310CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP QCPI Q’ 2 3 4 5 6 7 8 9 1 ..
CD74HC4040E ,High Speed CMOS Logic 12-Stage Binary CounterMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD74HC4040M ,High Speed CMOS Logic 12-Stage Binary CounterFeatures Description• Fully Static Operation The ’HC4040 and ’HCT4040 are 14-stage ripple-carrybina ..
CD74HC4040M ,High Speed CMOS Logic 12-Stage Binary CounterLogic Diagram310CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP QCPI Q’ 2 3 4 5 6 7 8 9 1 ..
CD74HC4040M96 ,High Speed CMOS Logic 12-Stage Binary CounterCD54HC4040, CD74HC4040,CD54HCT4040, CD74HCT4040Data sheet acquired from Harris SemiconductorSCHS203 ..
CKG57KX7R1C476M , Multilayer Ceramic Chip Capacitors
CL ,Wirewound Resistors, Commercial Power, Tab Type Terminals, Variety of core diameters and lengths, Numerous mounting hole sizes and shapes, High performance for low cost , contact ww2aresistors Document Number 3022244 Revision 04-Sep-02CLWirewound Resistors, Commercia ..
CL10C101JBNC , Multilayer Ceramic Capacitor
CD74HC4024E-CD74HC4024M-CD74HC4024PWR
High Speed CMOS Logic 7-Stage Binary Ripple Counter
CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024 SCHS202C High-Speed CMOS Logic November 1997 - Revised October 2003 7-Stage Binary Ripple Counter Features Description • Fully Static Operation The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The • Buffered Inputs [ /Title state of the stage advances one count on the negative (CD74 transition of each input pulse; a high voltage level on the MR • Common Reset line resets all counters to their zero state. All inputs and HC402 • Negative Edge Clocking outputs are buffered. 4, • Fanout (Over Temperature Range) CD74 Ordering Information - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads HCT40 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TEMP. RANGE 24) o PART NUMBER ( C) PACKAGE o o C to 125 C • Wide Operating Temperature Range . . . -55 /Sub- CD54HC4024F3A -55 to 125 14 Ld CERDIP ject • Balanced Propagation Delay and Transition Times (High CD54HCT4024F3A -55 to 125 14 Ld CERDIP • Significant Power Reduction Compared to LSTTL Speed Logic ICs CD74HC4024E -55 to 125 14 Ld PDIP CMOS • HC Types CD74HC4024M -55 to 125 14 Ld SOIC - 2V to 6V Operation CD74HC4024MT -55 to 125 14 Ld SOIC - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CC CD74HC4024M96 -55 to 125 14 Ld SOIC • HCT Types CD74HC4024PW -55 to 125 14 Ld TSSOP - 4.5V to 5.5V Operation CD74HC4024PWR -55 to 125 14 Ld TSSOP - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) IL IH CD74HC4024PWT -55 to 125 14 Ld TSSOP - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HCT4024E -55 to 125 14 Ld PDIP CD74HCT4024M -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC4024, CD54HCT4024 (CERDIP) CD74HC4024 (PDIP, SOIC, TSSOP) CD74HCT4024 (PDIP, SOIC) TOP VIEW CP 1 14 V CC MR 2 13 NC Q 3 12 Q ’ 7 1 Q 4 11 Q 6 2 Q 5 10 NC 5 Q 6 9 Q 4 3 8 NC GND 7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
