CD74HC4017NSR ,High Speed CMOS Logic Decade Counter/Divider with 10 Decoded OutputsFeatures DescriptionThe ’HC4017 is a high speed silicon gate CMOS 5-stage• Fully Static OperationJo ..
CD74HC4017PWR ,High Speed CMOS Logic Decade Counter/Divider with 10 Decoded OutputsMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD74HC4020E ,High Speed CMOS Logic 14-Stage Binary CounterMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC4024E ,7-stage binary ripple counterMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC4024M ,7-stage binary ripple counterFeatures Description• Fully Static Operation The ’HC4024 and ’HCT4024 are 7-stage ripple-carry bina ..
CD74HC4024M ,7-stage binary ripple counterLogic Diagram1CP Q CP Q CP Q CP Q CP Q CP Q CP QCP1 Q1 2 3 4 5 6 7CP Q CP Q CP Q CP Q CP Q CP Q CP ..
CKG57KX7R1C476M , Multilayer Ceramic Chip Capacitors
CL ,Wirewound Resistors, Commercial Power, Tab Type Terminals, Variety of core diameters and lengths, Numerous mounting hole sizes and shapes, High performance for low cost , contact ww2aresistors Document Number 3022244 Revision 04-Sep-02CLWirewound Resistors, Commercia ..
CL10C101JBNC , Multilayer Ceramic Capacitor
CD74HC4017E-CD74HC4017M-CD74HC4017M96-CD74HC4017NSR-CD74HC4017PWR
High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs
CD54HC4017, CD74HC4017 SCHS200D High-Speed CMOS Logic November 1997 - Revised October 2003 Decade Counter/Divider with 10 Decoded Outputs Features Description The ’HC4017 is a high speed silicon gate CMOS 5-stage • Fully Static Operation Johnson counter with 10 decoded outputs. Each of the • Buffered Inputs [ /Title decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock (CD74 • Common Reset period cycle. The CARRY (TC) output transitions low to high HC401 • Positive Edge Clocking after OUTPUT 10 goes from high to low, and can be used in 7) o conjunction with the CLOCK ENABLE (CE) to cascade = 50MHz at V =5V,C = 15pF, T =25 C • Typical f MAX CC L A /Sub- several stages. The CLOCK ENABLE input disables • Fanout (Over Temperature Range) counting when in the high state. A RESET (MR) input is also ject - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads provided which when taken high sets all the decoded (High outputs, except “0”, low. - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Speed o o The device can drive up to 10 low power Schottky equivalent • Wide Operating Temperature Range . . . -55 C to 125 C CMOS loads. Logic • Balanced Propagation Delay and Transition Times Decade Ordering Information • Significant Power Reduction Compared to LSTTL Counte Logic ICs TEMP. RANGE o • HC Types PART NUMBER ( C) PACKAGE - 2V to 6V Operation CD54HC4017F3A -55 to 125 16 Ld CERDIP - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CD74HC4017E -55 to 125 16 Ld PDIP CC CD74HC4017M -55 to 125 16 Ld SOIC CD74HC4017MT -55 to 125 16 Ld SOIC CD74HC4017M96 -55 to 125 16 Ld SOIC CD74HC4017NSR -55 to 125 16 Ld SOP CD74HC4017PW -55 to 125 16 Ld TSSOP CD74HC4017PWR -55 to 125 16 Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC4017 (CERDIP) CD74HC4017 (PDIP, SOIC, SOP, TSSOP) TOP VIEW 5 1 16 V CC 1 2 15 MR 0 3 14 CP 2 4 13 CE 6 5 12 TC 7 6 11 9 3 7 10 4 GND 8 9 8 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
