CD74HC40105M96 ,High-Speed CMOS Logic 4-Bit x 16-Word FIFO RegisterFeatures Description• Independent Asynchronous Inputs and Outputs The ’HC40105 and ’HCT40105 are hi ..
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CKG57KX7R1C476M , Multilayer Ceramic Chip Capacitors
CL ,Wirewound Resistors, Commercial Power, Tab Type Terminals, Variety of core diameters and lengths, Numerous mounting hole sizes and shapes, High performance for low cost , contact ww2aresistors Document Number 3022244 Revision 04-Sep-02CLWirewound Resistors, Commercia ..
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CD74HC40105E-CD74HC40105M-CD74HC40105M96
High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 SCHS222C High-Speed CMOS Logic February 1998 - Revised October 2003 4-Bit x 16-Word FIFO Register Features Description • Independent Asynchronous Inputs and Outputs The ’HC40105 and ’HCT40105 are high-speed silicon-gate CMOS devices that are compatible, except for “shift-out” • Expandable in Either Direction [ /Title circuitry, with the CD40105B. They are low-power first-in-out (CD74 (FIFO) “elastic” storage registers that can store 16 four-bit • Reset Capability words. The 40105 is capable of handling input and output HC401 • Status Indicators on Inputs and Outputs data at different shifting rates. This feature makes it 05, particularly useful as a buffer between asynchronous • Three-State Outputs CD74 systems. • Shift-Out Independent of Three-State Control HCT40 Each work position in the register is clocked by a control flip- 105) • Fanout (Over Temperature Range) flop, which stores a marker bit. A “1” signifies that the posi- tion’s data is filled and a “0” denotes a vacancy in that posi- /Sub- - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads tion. The control flip-flop detects the state of the preceding ject - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads flip-flop and communicates its own status to the succeeding (High o o C to 125 C flip-flop. When a control flip-flop is in the “0” state and sees a • Wide Operating Temperature Range . . . -55 Speed “1” in the preceeding flip-flop, it generates a clock pulse that • Balanced Propagation Delay and Transition Times transfers data from the preceding four data latches into its CMOS own four data latches and resets the preceding flip-flop to • Significant Power Reduction Compared to LSTTL “0”. The first and last control flip-flops have buffered outputs. Logic ICs Since all empty locations “bubble” automatically to the input • HC Types end, and all valid data ripple through to the output end, the - 2V to 6V Operation status of the first control flip-flop (DATA-IN READY) indicates = 30%, N = 30% of V if the FIFO is full, and the status of the last flip-flop (DATA- - High Noise Immunity: N IL IH CC at V = 5V OUT READY) indicates if the FIFO contains data. As the CC earliest data are removed from the bottom of the data stack • HCT Types (the output end), all data entered later will automatically - 4.5V to 5.5V Operation propagate (ripple) toward the output. - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) Ordering Information IL IH ≤ 1µA at V , V - CMOS Input Compatibility, I l OL OH o PART NUMBER TEMP. RANGE ( C) PACKAGE Applications CD54HC40105F3A -55 to 125 16 Ld CERDIP • Bit-Rate Smoothing CD54HCT40105F3A -55 to 125 16 Ld CERDIP • CPU/Terminal Buffering CD74HC40105E -55 to 125 16 Ld PDIP • Data Communications CD74HC40105M -55 to 125 16 Ld SOIC • Peripheral Buffering CD74HC40105MT -55 to 125 16 Ld SOIC • Line Printer Input Buffers CD74HC40105M96 -55 to 125 16 Ld SOIC • Auto-Dialers CD74HCT40105E -55 to 125 16 Ld PDIP • CRT Buffer Memories CD74HCT40105M -55 to 125 16 Ld SOIC • Radar Data Acquisition CD74HCT40105MT -55 to 125 16 Ld SOIC CD74HCT40105M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
