CD74HC299M96G4 ,High Speed CMOS Logic 8-Bit Universal Shift Register with 3-State Outputs 20-SOIC -55 to 125Maximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC30E ,High Speed CMOS Logic 8-Input NAND GateMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD74HC30M ,High Speed CMOS Logic 8-Input NAND Gate CD54/74HC30,CD54/74HCT30Data sheet acquired from Harris SemiconductorSCHS121DHigh Speed CMOS Logic ..
CD74HC30M ,High Speed CMOS Logic 8-Input NAND Gate CD54/74HC30,CD54/74HCT30Data sheet acquired from Harris SemiconductorSCHS121DHigh Speed CMOS Logic ..
CD74HC30M96 ,High Speed CMOS Logic 8-Input NAND GateFeatures Description• Buffered Inputs The ’HC30 and ’HCT30 each contain an 8-input NAND gatein one ..
CD74HC30M96G4 ,High Speed CMOS Logic 8-Input NAND Gate 14-SOIC -55 to 125Maximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CKG57KX7R1C476M , Multilayer Ceramic Chip Capacitors
CL ,Wirewound Resistors, Commercial Power, Tab Type Terminals, Variety of core diameters and lengths, Numerous mounting hole sizes and shapes, High performance for low cost , contact ww2aresistors Document Number 3022244 Revision 04-Sep-02CLWirewound Resistors, Commercia ..
CL10C101JBNC , Multilayer Ceramic Capacitor
CD74HC299E-CD74HC299M-CD74HC299M96G4
High Speed CMOS Logic 8-Bit Universal Shift Register with 3-State Outputs
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 SCHS178C High-Speed CMOS Logic January 1998 - Revised May 2003 8-Bit Universal Shift Register; Three-State Features Description The ’HC259 and ’HCT299 are 8-bit shift/storage registers • Buffered Inputs with three-state bus interface capability. The register has four synchronous-operating modes controlled by the two select • Four Operating Modes: Shift Left, Shift Right, Load [ /Title and Store inputs as shown in the mode select (S0, S1) table. The mode (CD74 select, the serial data (DS0, DS7) and the parallel data (I/O 0 • Can be Cascaded for N-Bit Word Lengths HC299 - I/O ) respond only to the low-to-high transition of the clock 7 (CP) pulse. S0, S1 and data inputs must be stable one set- , - I/O Bus Drive Capability and Three-State for • I/O 0 7 up time prior to the clock positive transition. Bus Oriented Applications CD74 o The Master Reset (MR) is an asynchronous active low input. HCT29 • Typical f = 50MHz at V =5V,C = 15pF, T =25 C MAX CC L A When MR output is low, the register is cleared regardless of 9) • Fanout (Over Temperature Range) the status of all other inputs. The register can be expanded /Sub- - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads by cascading same units by tying the serial output (Q0) to ject - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of (High o o • Wide Operating Temperature Range . . . -55 C to 125 C the following register. Recirculating the (n x 8) bits is Speed accomplished by tying the Q7 of the last stage to the DS0 of • Balanced Propagation Delay and Transition Times CMOS the first stage. • Significant Power Reduction Compared to LSTTL Logic The three-state input/output I(/O) port has three modes of Logic ICs 8-Bit operation: • HC Types Uni- 1. Both output enable (OE1 and OE2) inputs are low and S0 - 2V to 6V Operation versal or S1 or both are low, the data in the register is presented - High Noise Immunity: N = 30%, N = 30% of V IL IH CC Shift at the eight outputs. at V = 5V CC 2. When both S0 and S1 are high, I/O terminals are in the • HCT Types high impedance state but being input ports, ready for par- - 4.5V to 5.5V Operation allel data to be loaded into eight registers with one clock transition regardless of the status of OE1 and OE2. - Direct LSTTL Input Logic Compatibility, = 0.8V (Max), V = 2V (Min) V IL IH 3. Either one of the two output enable inputs being high will - CMOS Input Compatibility, I ≤ 1μA at V , V l OL OH force I/O terminals to be in the off-state. It is noted that each I/O terminal is a three-state output and a CMOS buffer input. Pinout Ordering Information CD54HC299, CD54HCT299 (CERDIP) o PART NUMBER TEMP. RANGE ( C) PACKAGE CD74HC299, CD74HCT299 (PDIP, SOIC) CD54HC299F3A -55 to 125 20 Ld CERDIP TOP VIEW CD54HCT299F3A -55 to 125 20 Ld CERDIP S0 1 20 V CC CD74HC299E -55 to 125 20 Ld PDIP OE1 2 S1 19 CD74HC299M -55 to 125 20 Ld SOIC OE2 3 18 DS7 CD74HC299M96 -55 to 125 20 Ld SOIC I/O 4 17 Q7 6 I/O 5 16 I/O 4 7 CD74HCT299E -55 to 125 20 Ld PDIP I/O 6 15 I/O 2 5 CD74HCT299M -55 to 125 20 Ld SOIC I/O 7 14 I/O 0 3 CD74HCT299M96 -55 to 125 20 Ld SOIC Q0 8 13 I/O 1 NOTE: When ordering, use the entire part number. The suffix 96 MR 9 12 CP denotes tape and reel. GND 10 11 DS0 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
