CD74HC297E ,High Speed CMOS Logic Digital Phase-Locked-LoopFeatures Description• Digital Design Avoids Analog Compensation Errors The ’HC297 and CD74HCT297 ar ..
CD74HC297E ,High Speed CMOS Logic Digital Phase-Locked-LoopCD54HC297, CD74HC297,CD74HCT297Data sheet acquired from Harris SemiconductorHigh-Speed CMOS LogicSC ..
CD74HC297E ,High Speed CMOS Logic Digital Phase-Locked-LoopMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC299E ,High Speed CMOS Logic 8-Bit Universal Shift Register with 3-State OutputsMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC299M ,High Speed CMOS Logic 8-Bit Universal Shift Register with 3-State OutputsFeatures DescriptionThe ’HC259 and ’HCT299 are 8-bit shift/storage registers• Buffered Inputswith t ..
CD74HC299M ,High Speed CMOS Logic 8-Bit Universal Shift Register with 3-State OutputsFeatures DescriptionThe ’HC259 and ’HCT299 are 8-bit shift/storage registers• Buffered Inputswith t ..
CKG57KX7R1C476M , Multilayer Ceramic Chip Capacitors
CL ,Wirewound Resistors, Commercial Power, Tab Type Terminals, Variety of core diameters and lengths, Numerous mounting hole sizes and shapes, High performance for low cost , contact ww2aresistors Document Number 3022244 Revision 04-Sep-02CLWirewound Resistors, Commercia ..
CL10C101JBNC , Multilayer Ceramic Capacitor
CD74HC297E
High Speed CMOS Logic Digital Phase-Locked-Loop
CD54HC297, CD74HC297, CD74HCT297 High-Speed CMOS Logic SCHS177B Digital Phase-Locked Loop November 1997 - Revised May 2003 Features Description • Digital Design Avoids Analog Compensation Errors The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schot- • Easily Cascadable for Higher Order Loops [ /Title tky TTL (LSTTL). • Useful Frequency Range (CD74 These devices are designed to provide a simple, cost-effec- - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) HC297 tive solution to high-accuracy, digital, phase-locked-loop appli- - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) cations. They contain all the necessary circuits, with the , exception of the divide-by-N counter, to build first-order • Dynamically Variable Bandwidth CD74 phase-locked-loops. HCT29 • Very Narrow Bandwidth Attainable Both EXCLUSIVE-OR (XORPD) and edge-controlled phase 7) • Power-On Reset detectors (ECPD) are provided for maximum flexibility. The /Sub- input signals for the EXCLUSIVE-OR phase detector must • Output Capability ject have a 50% duty factor to obtain the maximum lock-range. , ECPD - Standard . . . . . . . . . . . . . . . . . . . . XORPD OUT OUT (High- Proper partitioning of the loop function, with many of the build- - Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/D OUT ing blocks external to the package, makes it easy for the Speed • Fanout (Over Temperature Range) designer to incorporate ripple cancellation (see Figure 2) or to CMOS - Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads cascade to higher order phase-locked-loops. Logic - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The length of the up/down K-counter is digitally programmable Digi- • Balanced Propagation Delay and Transition Times according to the K-counter function table. With A, B, C and D tal all LOW, the K-counter is disabled. With A HIGH and B, C and • Significant Power Reduction Compared to LSTTL D LOW, the K-counter is only three stages long, which widens Phase- Logic ICs the bandwidth or capture range and shortens the lock time of Locked • ’HC297 Types the loop. When A, B, C and D are all programmed HIGH, the - Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. = 30%, N = 30% of V at 5V - High Noise Immunity N IL IH CC Real-time control of loop bandwidth by manipulating the A to • CD74HCT297 Types D inputs can maximize the overall performance of the digital - Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V phase-locked-loop. - Direct LSTTL Input Logic Compatibility The ’HC297 and CD74HCT297 can perform the classic first V = 0.8V (Max), V = 2V (Min) IL IH order phase-locked-loop function without using analog com- - CMOS Input Compatibility I ≤ 1μA at V , V I OL OH ponents. The accuracy of the digital phase-locked-loop (DPLL) is not affected by V and temperature variations but CC Pinout depends solely on accuracies of the K-clock and loop propa- gation delays. CD54HC297 (CERDIP) CD74HC297, CD74HCT29 (PDIP) Ordering Information TOP VIEW o PART NUMBER TEMP. RANGE ( C) PACKAGE 16 V B 1 CC CD54HC297F3A -55 to 125 16 Ld CERDIP A 2 15 C CD74HC297E -55 to 125 16 Ld PDIP EN 3 14 D CTR CD74HCT297E -55 to 125 16 Ld PDIP K 4 13 φA CP 2 I/D 5 12 ECPD CP OUT D/U 6 11 XORPD OUT I/D 7 10 φB OUT GND 8 9 φA 1 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
