CD74HC280M96 ,High Speed CMOS Logic 9-Bit Odd/Even Parity Generator/CheckerFeatures Description• Typical Propagation Delay = 17ns at V = 5V, The ’HC280 and ’HCT280 are 9-bit ..
CD74HC283E ,High Speed CMOS Logic 4-Bit Binary Full Adder with Fast CarryCD54HC283, CD74HC283,CD54HCT283, CD74HCT283Data sheet acquired from Harris SemiconductorSCHS176DHig ..
CD74HC283M ,High Speed CMOS Logic 4-Bit Binary Full Adder with Fast CarryMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD74HC297E ,High Speed CMOS Logic Digital Phase-Locked-LoopFeatures Description• Digital Design Avoids Analog Compensation Errors The ’HC297 and CD74HCT297 ar ..
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CKG57KX7R1C476M , Multilayer Ceramic Chip Capacitors
CL ,Wirewound Resistors, Commercial Power, Tab Type Terminals, Variety of core diameters and lengths, Numerous mounting hole sizes and shapes, High performance for low cost , contact ww2aresistors Document Number 3022244 Revision 04-Sep-02CLWirewound Resistors, Commercia ..
CL10C101JBNC , Multilayer Ceramic Capacitor
CD74HC280E-CD74HC280M96
High Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker
CD54HC280, CD74HC280, CD54HCT280, CD74HCT280 SCHS175D High-Speed CMOS Logic November 1997 - Revised October 2003 9-Bit Odd/Even Parity Generator/Checker Features Description • Typical Propagation Delay = 17ns at V = 5V, The ’HC280 and ’HCT280 are 9-bit odd/even parity, generator CC o C = 15pF, T = 25 C checker devices. Both even and odd parity outputs are L A [ /Title available for checking or generating parity for words up to nine • Replaces LS180 Types (CD74 bits long. Even parity is indicated (ΣE output is high) when an even number of data inputs is high. Odd parity is indicated • Easily Cascadable HC280 (ΣO output is high) when an odd number of data inputs is , • Fanout (Over Temperature Range) high. Parity checking for words larger than 9 bits can be D74 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads C accomplished by tying the ΣE output to any input of an - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads additional HC/HCT280 parity checker. HCT28 o o • Wide Operating Temperature Range . . . -55 C to 125 C 0) Ordering Information /Sub- • Balanced Propagation Delay and Transition Times TEMP. RANGE ject o • Significant Power Reduction Compared to LSTTL PART NUMBER ( C) PACKAGE (High Logic ICs CD54HC280F3A -55 to 125 14 Ld CERDIP Speed • HC Types CD54HCT280F3A -55 to 125 14 Ld CERDIP CMOS - 2V to 6V Operation CD74HC280E -55 to 125 14 Ld PDIP - High Noise Immunity: N = 30%, N = 30% of V Logic IL IH CC at V = 5V CC CD74HC280MT -55 to 125 14 Ld SOIC 9-Bit • HCT Types Odd/E CD74HC280M96 -55 to 125 14 Ld SOIC - 4.5V to 5.5V Operation ven CD74HCT280E -55 to 125 14 Ld PDIP - Direct LSTTL Input Logic Compatibility, Parity V = 0.8V (Max), V = 2V (Min) IL IH NOTE: When ordering, use the entire part number. The suffix 96 - CMOS Input Compatibility, I ≤ 1µA at V , V denotes tape and reel. The suffix T denotes a small-quantity reel l OL OH of 250. Pinout Functional Diagram CD54HC280, CD54HCT280 8 (CERDIP) I0 CD74HC280 9 (PDIP, SOIC) I1 CD74HCT280 10 I2 (PDIP) 5 ∑ EVEN TOP VIEW 11 I3 12 I6 1 14 V CC I4 6 ∑ ODD I7 2 13 I5 13 I5 NC 3 12 I4 1 I6 I8 4 11 I3 2 I7 ΣE 5 10 I2 GND = 7 4 V = 14 CC I8 ΣO 6 9 I1 NC = 3 GND 7 8 I0 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
