CD74HC259E ,High Speed CMOS Logic 8-Bit Addressable Latchfeatures thelow-power consumption associated with CMOS circuitry and• Four Operating Modes[ /Titleh ..
CD74HC259E ,High Speed CMOS Logic 8-Bit Addressable LatchMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC259E ,High Speed CMOS Logic 8-Bit Addressable LatchFeatures Description• Buffered Inputs and Outputs The ’HC259 and ’HCT259 Addressable Latch
CD74HC259M ,High Speed CMOS Logic 8-Bit Addressable LatchCD54HC259, CD74HC259,CD54HCT259, CD74HCT259Data sheet acquired from Harris SemiconductorSCHS173CHig ..
CD74HC259M ,High Speed CMOS Logic 8-Bit Addressable Latchfeatures thelow-power consumption associated with CMOS circuitry and• Four Operating Modes[ /Titleh ..
CD74HC259M96 ,High Speed CMOS Logic 8-Bit Addressable LatchMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CKG57KX7R1C476M , Multilayer Ceramic Chip Capacitors
CL ,Wirewound Resistors, Commercial Power, Tab Type Terminals, Variety of core diameters and lengths, Numerous mounting hole sizes and shapes, High performance for low cost , contact ww2aresistors Document Number 3022244 Revision 04-Sep-02CLWirewound Resistors, Commercia ..
CL10C101JBNC , Multilayer Ceramic Capacitor
CD74HC259E-CD74HC259M-CD74HC259M96
High Speed CMOS Logic 8-Bit Addressable Latch
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 SCHS173C High-Speed CMOS Logic November 1997 - Revised October 2003 8-Bit Addressable Latch Features Description • Buffered Inputs and Outputs The ’HC259 and ’HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and • Four Operating Modes [ /Title has speeds comparable to low-power Schottky. (CD74 = 5V, • Typical Propagation Delay of 15ns at V CC This latches three active modes and one reset mode. When o C = 15pF, T = 25 C HC259 L A both the Latch Enable (LE) and Master Reset (MR) inputs are , low (8-line Demultiplexer mode) the output of the addressed • Fanout (Over Temperature Range) latch follows the Data input and all other outputs are forced D74 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads C low. When both MR and LE are high (Memory Mode), all - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads HCT25 outputs are isolated from the Data input, i.e., all latches hold o o 9) • Wide Operating Temperature Range . . . -55 C to 125 C the last data presented before the LE transition from low to high. A condition of LE low and MR high (Addressable Latch /Sub- • Balanced Propagation Delay and Transition Times mode) allows the addressed latch’s output to follow the data ject input; all other latches are unaffected. The Reset mode (all • Significant Power Reduction Compared to LSTTL (High outputs low) results when LE is high and MR is low. Logic ICs Speed • HC Types Ordering Information CMOS - 2V to 6V Operation Logic - High Noise Immunity: N = 30%, N = 30% of V TEMP. RANGE IL IH CC 8-Bit o at V = 5V PART NUMBER ( C) PACKAGE CC Addres • HCT Types CD54HC259F3A -55 to 125 16 Ld CERDIP sable - 4.5V to 5.5V Operation CD54HCT259F3A -55 to 125 16 Ld CERDIP Latch) - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) CD74HC259E -55 to 125 16 Ld PDIP IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HC259M -55 to 125 16 Ld SOIC CD74HC259MT -55 to 125 16 Ld SOIC CD74HC259M96 -55 to 125 16 Ld SOIC CD74HCT259E -55 to 125 16 Ld PDIP CD74HCT259M -55 to 125 16 Ld SOIC CD74HCT259MT -55 to 125 16 Ld SOIC CD74HCT259M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
