CD74HC20E ,High Speed CMOS Logic Dual 4-Input NAND GatesFeatures Description• Buffered Inputs The ’HC20 and ’HCT20 logic gates utilize silicon gate CMOStec ..
CD74HC20E ,High Speed CMOS Logic Dual 4-Input NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC20E ,High Speed CMOS Logic Dual 4-Input NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC20E ,High Speed CMOS Logic Dual 4-Input NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD74HC20M96 ,High Speed CMOS Logic Dual 4-Input NAND GatesFeatures Description• Buffered Inputs The ’HC20 and ’HCT20 logic gates utilize silicon gate CMOStec ..
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CL ,Wirewound Resistors, Commercial Power, Tab Type Terminals, Variety of core diameters and lengths, Numerous mounting hole sizes and shapes, High performance for low cost , contact ww2aresistors Document Number 3022244 Revision 04-Sep-02CLWirewound Resistors, Commercia ..
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CD74HC20-CD74HC20E-CD74HC20M-CD74HC20M96-CD74HC20M96G4
High Speed CMOS Logic Dual 4-Input NAND Gates
CD54HC20, CD74HC20, CD54HCT20, CD74HCT20 SCHS130C High-Speed CMOS Logic August 1997 - Revised September 2003 Dual 4-Input NAND Gate Features Description • Buffered Inputs The ’HC20 and ’HCT20 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL = 5V, • Typical Propagation Delay: 8ns at V [ /Title CC gates with the low power consumption of standard CMOS o C = 15pF, T = 25 C L A (CD74H integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin • Fanout (Over Temperature Range) C20, compatible with the standard LS logic family. - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads CD74H - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CT20) Ordering Information o o • Wide Operating Temperature Range . . . -55 C to 125 C /Subject TEMP. RANGE (High • Balanced Propagation Delay and Transition Times o PART NUMBER ( C) PACKAGE Speed • Significant Power Reduction Compared to LSTTL CD54HC20F3A -55 to 125 14 Ld CERDIP CMOS Logic ICs Logic CD54HCT20F3A -55 to 125 14 Ld CERDIP • HC Types Dual 4- - 2V to 6V Operation CD74HC20E -55 to 125 14 Ld PDIP Input - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC20M -55 to 125 14 Ld SOIC at V = 5V CC CD74HC20MT -55 to 125 14 Ld SOIC • HCT Types - 4.5V to 5.5V Operation CD74HC20M96 -55 to 125 14 Ld SOIC - Direct LSTTL Input Logic Compatibility, CD74HCT20E -55 to 125 14 Ld PDIP V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V CD74HCT20M -55 to 125 14 Ld SOIC l OL OH CD74HCT20MT -55 to 125 14 Ld SOIC CD74HCT20M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC20, CD54HCT20 (CERDIP) CD74HC20, CD74HCT20 (PDIP, SOIC) TOP VIEW 1A 1 14 V CC 1B 2 13 2D NC 3 12 2C 1C 4 11 NC 1D 5 10 2B 1Y 6 9 2A GND 7 8 2Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
