CD74HC194E ,High Speed CMOS Logic 4-Bit Bidirectional Universal Shift RegisterFeatures Description• Four Operating Modes The ’HC194 and CD74HCT194 are 4-bit shift registers with ..
CD74HC194M96 ,High Speed CMOS Logic 4-Bit Bidirectional Universal Shift RegisterMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD74HC194NSR , High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register
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CD74HC20 ,High Speed CMOS Logic Dual 4-Input NAND GatesFeatures Description• Buffered Inputs The ’HC20 and ’HCT20 logic gates utilize silicon gate CMOStec ..
CD74HC20E ,High Speed CMOS Logic Dual 4-Input NAND GatesFeatures Description• Buffered Inputs The ’HC20 and ’HCT20 logic gates utilize silicon gate CMOStec ..
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CK2125100M-T , Multilayer Chip Inductors (CK series / CK series S type)
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CD74HC193E
High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counter with Asynchronous Reset
CD54/74HC192, CD54/74HC193, CD54/74HCT193 SCHS163F High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters September 1997 - Revised October 2003 Presetting the counter to the number on the preset data inputs Features (P0-P3) is accomplished by a LOW asynchronous parallel • Synchronous Counting and Asynchronous load input (PL). The counter is incremented on the low-to-high Loading transition of the Clock-Up input (and a high level on the Clock- [ /Title Down input) and decremented on the low to high transition of • Two Outputs for N-Bit Cascading (CD74 the Clock-Down input (and a high level on the Clock-up input). • Look-Ahead Carry for High-Speed Counting A high level on the MR input overrides any other input to clear HC192 the counter to its zero state. The Terminal Count up (carry) , • Fanout (Over Temperature Range) goes low half a clock period before the zero count is reached - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads D74 C and returns to a high level at the zero count. The Terminal - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads HC193 Count Down (borrow) in the count down mode likewise goes o o low half a clock period before the maximum count (9 in the • Wide Operating Temperature Range . . . -55 C to 125 C , 192 and 15 in the 193) and returns to high at the maximum D74 C • Balanced Propagation Delay and Transition Times count. Cascading is effected by connecting the carry and HCT19 borrow outputs of a less significant counter to the Clock-Up • Significant Power Reduction Compared to LSTTL 3) Logic ICs and Clock-Down inputs, respectively, of the next most significant counter. /Sub- • HC Types ject - 2V to 6V Operation If a decade counter is preset to an illegal state or assumes an - High Noise Immunity: N = 30%, N = 30% of V illegal state when power is applied, it will return to the normal (High IL IH CC at V = 5V sequence in one count as shown in state diagram. CC Speed • HCT Types CMOS Ordering Information - 4.5V to 5.5V Operation Logic - Direct LSTTL Input Logic Compatibility, TEMP. RANGE Preset- V = 0.8V (Max), V = 2V (Min) IL IH o PART NUMBER ( C) PACKAGE - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD54HC192F3A -55 to 125 16 Ld CERDIP Description CD54HC193F3A -55 to 125 16 Ld CERDIP The ’HC192, ’HC193 and ’HCT193 are asynchronously CD54HCT193F3A -55 to 125 16 Ld CERDIP presettable BCD Decade and Binary Up/Down synchronous CD74HC192E -55 to 125 16 Ld PDIP counters, respectively. CD74HC192NSR -55 to 125 16 Ld SOP CD74HC192PW -55 to 125 16 Ld TSSOP Pinout CD74HC192PWR -55 to 125 16 Ld TSSOP CD54HC192, CD54HC193, CD54HCT193 (CERDIP) CD74HC192 (PDIP, SOP, TSSOP) CD74HC192PWT -55 to 125 16 Ld TSSOP CD74HC193 (PDIP, SOIC) CD74HCT193 (PDIP) CD74HC193E -55 to 125 16 Ld PDIP TOP VIEW CD74HC193M -55 to 125 16 Ld SOIC P1 1 16 V CC CD74HC193MT -55 to 125 16 Ld SOIC Q1 2 15 P0 CD74HC193M96 -55 to 125 16 Ld SOIC Q0 3 14 MR CPD 4 13 TCD CD74HCT193E -55 to 125 16 Ld PDIP CPU 5 12 TCU NOTE: When ordering, use the entire part number. The suffixes 96 Q2 6 11 PL and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Q3 7 10 P2 GND 8 9 P3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
