CD74HC191M ,High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counterslogic diagramA B15114bCLK5D/U c11LOAD defghiLOAD LOADDATADATAT jQ T QCLKQCLKQFF0 FF1klmno4pCTEN32Q ..
CD74HC192E ,High Speed CMOS Logic Presettable Synchronous BCD Decade Up/Down Counter with Asynchronous ResetFeatures(P0-P3) is accomplished by a LOW asynchronous parallel• Synchronous Counting and Asynchrono ..
CD74HC192E ,High Speed CMOS Logic Presettable Synchronous BCD Decade Up/Down Counter with Asynchronous ResetFeatures(P0-P3) is accomplished by a LOW asynchronous parallel• Synchronous Counting and Asynchrono ..
CD74HC192E ,High Speed CMOS Logic Presettable Synchronous BCD Decade Up/Down Counter with Asynchronous ResetMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD74HC192NSR ,High Speed CMOS Logic Presettable Synchronous BCD Decade Up/Down Counter with Asynchronous ResetCD54/74HC192,CD54/74HC193, CD54/74HCT193Data sheet acquired from Harris SemiconductorSCHS163F High- ..
CD74HC192PW , High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters
CJS-1200TB1 , SLIDE SWITCHES(SMD)
CJU1117-1.8 , 1A LOW DROPOUT LINEAR REGULATOR
CJU1117-2.5 , 1A LOW DROPOUT LINEAR REGULATOR
CJU1117-5.0 , 1A LOW DROPOUT LINEAR REGULATOR
CK2125100M-T , Multilayer Chip Inductors (CK series / CK series S type)
CK2125100M-T , Multilayer Chip Inductors (CK series / CK series S type)
CD74HC191-CD74HC191E-CD74HC191M
High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counters
Synchronous Counting and AsynchronousLoading Two Outputs for n-Bit Cascading Look-Ahead Carry for High-Speed Counting Balanced Propagation Delays and
Transition Times Standard Outputs Drive Up To 15 LS-TTL
Loads Significant Power Reduction Compared to
LS-TTL Logic ICs
description/ordering informationThe CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and
CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A−D) is accomplished by a low asynchronous
parallel load (LOAD) input. Counting occurs when LOAD is high, count enable (CTEN) is low, and the down/up
(D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented
synchronously with the low-to-high transition of the clock.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
