CD74HC166M ,High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift RegisterCD54HC166, CD74HC166,CD54HCT166, CD74HCT166Data sheet acquired from Harris SemiconductorSCHS157CHig ..
CD74HC166M96 ,High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift RegisterFeatures Description• Buffered Inputs The ’HC166 and ’HCT166 8-bit shift register is fabricatedwith ..
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CD74HC166E-CD74HC166M-CD74HC166M96-CD74HC166MG4
High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166 SCHS157C High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register February 1998 - Revised October 2003 Features Description • Buffered Inputs The ’HC166 and ’HCT166 8-bit shift register is fabricated with silicon gate CMOS technology. It possesses the low • Fanout (Over Temperature Range) [ /Title power consumption of standard CMOS integrated circuits, - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads (CD74 and can operate at speeds comparable to the equivalent low - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads power Schottky device. HC166 o o C to 125 C • Wide Operating Temperature Range . . . -55 , The ’HCT166 is functionally and pin compatible with the • Balanced Propagation Delay and Transition Times standard ’LS166. D74 C • Significant Power Reduction Compared to LSTTL HCT16 The 166 is an 8-bit shift register that has fully synchronous Logic ICs serial or parallel data entry selected by an active LOW Parallel 6) • HC Types Enable (PE) input. When the PE is LOW one setup time before /Sub- - 2V to 6V Operation the LOW-to-HIGH clock transition, parallel data is entered into ject = 30%, N = 30% of V the register. When PE is HIGH, data is entered into the internal - High Noise Immunity: N IL IH CC at V = 5V bit position Q0 from Serial Data Input (DS), and the remaining (High CC • HCT Types bits are shifted one place to the right (Q0 → Q1 → Q2, etc.) Speed - 4.5V to 5.5V Operation with each positive-going clock transition. For expansion of the CMOS - Direct LSTTL Input Logic Compatibility, register in parallel to serial converters, the Q7 output is con- Logic V = 0.8V (Max), V = 2V (Min) nected to the DS input of the succeeding stage. IL IH 8-Bit The clock input is a gated OR structure which allows one Paral- input to be used as an active LOW Clock Enable (CE) input. Pinout The pin assignment for the CP and CE inputs is arbitrary and lel- can be reversed for layout convenience. The LOW-to-HIGH CD54HC166, CD54HCT166 In/Seri transition of CE input should only take place while the CP is (CERDIP) HIGH for predictable operation. CD74HC166, CD74HCT166 (PDIP, SOIC) A LOW on the Master Reset (MR) input overrides all other TOP VIEW inputs and clears the register asynchronously, forcing all bit positions to a LOW state. 16 V DS 1 CC D0 2 15 PE Ordering Information D1 3 14 D7 o D2 4 13 Q7 PART NUMBER TEMP. RANGE ( C) PACKAGE D3 5 12 D6 CD54HC166F3A -55 to 125 16 Ld CERDIP CE 6 11 D5 CD54HCT166F3A -55 to 125 16 Ld CERDIP CP 7 10 D4 CD74HC166E -55 to 125 16 Ld PDIP GND 8 9 MR CD74HC166M -55 to 125 16 Ld SOIC CD74HC166MT -55 to 125 16 Ld SOIC CD74HC166M96 -55 to 125 16 Ld SOIC CD74HCT166E -55 to 125 16 Ld PDIP CD74HCT166M -55 to 125 16 Ld SOIC CD74HCT166MT -55 to 125 16 Ld SOIC CD74HCT166M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
