CD74HC165M96 ,High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift RegisterMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC165M96G4 ,High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register 16-SOIC -55 to 125Maximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC166E ,High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift RegisterMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC166M ,High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift RegisterCD54HC166, CD74HC166,CD54HCT166, CD74HCT166Data sheet acquired from Harris SemiconductorSCHS157CHig ..
CD74HC166M96 ,High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift RegisterFeatures Description• Buffered Inputs The ’HC166 and ’HCT166 8-bit shift register is fabricatedwith ..
CD74HC166MG4 ,High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register 16-SOIC -55 to 125Features Description• Buffered Inputs The ’HC166 and ’HCT166 8-bit shift register is fabricatedwith ..
CJA1117-1.8 , 1A LOW DROPOUT LINEAR REGULATOR
CJA1117-2.5 , 1A LOW DROPOUT LINEAR REGULATOR
CJA1117-3.3 , 1A LOW DROPOUT LINEAR REGULATOR
CJA1117-5.0 , 1A LOW DROPOUT LINEAR REGULATOR
CJA1117-ADJ , 1A LOW DROPOUT LINEAR REGULATOR
CJB1117-3.3 , 1A LOW DROPOUT LINEAR REGULATOR
CD74HC165E-CD74HC165M-CD74HC165M96-CD74HC165M96G4
High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 SCHS156C High-Speed CMOS Logic February 1998 - Revised October 2003 8-Bit Parallel-In/Serial-Out Shift Register Features Description • Buffered Inputs The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift registers with complementary serial outputs (Q and Q ) 7 7 • Asynchronous Parallel Load [ /Title available from the last stage. When the parallel load (PL) (CD74H input is LOW, parallel data from the D0 to D7 inputs are • Complementary Outputs loaded into the register asynchronously. When the PL is C165, • Fanout (Over Temperature Range) HIGH, data enters the register serially at the DS input and CD74H - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads shifts one place to the right (Q →Q →Q , etc.) with each 0 1 2 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CT165) positive-going clock transition. This feature allows parallel- o o to-serial converter expansion by typing the Q output to the /Subject • Wide Operating Temperature Range . . . -55 C to 125 C 7 DS input of the succeeding device. (High • Balanced Propagation Delay and Transition Times For predictable operation the LOW-to-HIGH transition of CE Speed • Significant Power Reduction Compared to LSTTL should only take place while CP is HIGH. Also, CP an d CE CMOS Logic ICs should be LOW before the LOW-to-HIGH transition of PL to Logic 8- • HC Types prevent shifting the data when PL goes HIGH. Bit Par- - 2V to 6V Operation - High Noise Immunity: N = 30%, N = 30% of V Ordering Information allel- IL IH CC at V = 5V CC TEMP. RANGE • HCT Types o PART NUMBER ( C) PACKAGE - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, CD54HC165F3A -55 to 125 16 Ld CERDIP V = 0.8V (Max), V = 2V (Min) IL IH CD54HCT165F3A -55 to 125 16 Ld CERDIP - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HC165E -55 to 125 16 Ld PDIP CD74HC165M -55 to 125 16 Ld SOIC Pinout CD74HC165MT -55 to 125 16 Ld SOIC CD54HC165, CD54HCT165 (CERDIP) CD54HC165M96 -55 to 125 16 Ld SOIC CD74HC165, CD74HCT165 (PDIP, SOIC) CD74HCT165E -55 to 125 16 Ld PDIP TOP VIEW CD74HCT165M -55 to 125 16 Ld SOIC PL 1 16 V CC CD74HCT165MT -55 to 125 16 Ld SOIC CP 2 15 CE CD54HCT165M96 -55 to 125 16 Ld SOIC D4 3 14 D3 D5 4 13 D2 NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of D6 5 12 D1 250. D7 6 11 D0 Q 7 10 DS 7 GND 8 9 Q 7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
