CD74HC161M96 ,High Speed CMOS Logic 4-Bit Binary Counter with Asynchronous ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC163E ,High Speed CMOS Logic 4-Bit Binary Counter with Synchronous ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC163M96 ,High Speed CMOS Logic 4-Bit Binary Counter with Synchronous ResetCD54/74HC161, CD54/74HCT161,The CD54HCT161 is obsoleteand no longer is supplied.CD54/74HC163, CD54/ ..
CD74HC164E ,High Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift RegisterMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC164EE4 ,High Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift Register 14-PDIP -55 to 125Maximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC164M ,High Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift RegisterCD54HC164, CD74HC164,CD54HCT164, CD74HCT164Data sheet acquired from Harris SemiconductorSCHS155CHig ..
CJ78M09 , Three-terminal positive voltage regulator
CJ78M09 , Three-terminal positive voltage regulator
CJ78M09 , Three-terminal positive voltage regulator
CJ7915 , Three-terminal positive voltage regulator
CJ79L05 , Three-terminal negative voltage regulator
CJ79L05 , Three-terminal negative voltage regulator
CD74HC161E-CD74HC161M96
High Speed CMOS Logic 4-Bit Binary Counter with Asynchronous Reset
CD54/74HC161, CD54/74HCT161, The CD54HCT161 is obsolete and no longer is supplied. CD54/74HC163, CD54/74HCT163 SCHS154D High-Speed CMOS Logic February 1998 - Revised October 2003 Presettable Counters Two count enables, PE and TE, in each counter are Features provided for n-bit cascading. In all counters reset action • ’HC161, ’HCT161 4-Bit Binary Counter, occurs regardless of the level of the SPE, PE and TE inputs Asynchronous Reset (and the clock input, CP, in the ’HC161 and ’HCT161 [ /Title types). • ’HC163, ’HCT163 4-Bit Binary Counter, (CD74 Synchronous Reset If a decade counter is preset to an illegal state or assumes HC161 an illegal state when power is applied, it will return to the • Synchronous Counting and Loading , normal sequence in one count as shown in state diagram. • Two Count Enable Inputs for n-Bit Cascading D74 C The look-ahead carry feature simplifies serial cascading of • Look-Ahead Carry for High-Speed Counting HCT16 the counters. Both count enable inputs (PE and TE) must • Fanout (Over Temperature Range) be high to count. The TE input is gated with the Q outputs 1, - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads of all four stages so that at the maximum count the terminal CD74 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads count (TC) output goes high for one clock period. This TC HC163 o o pulse is used to enable the next cascaded stage. C to 125 C • Wide Operating Temperature Range . . . -55 , • Balanced Propagation Delay and Transition Times D74 C Ordering Information • Significant Power Reduction Compared to LSTTL HCT16 Logic ICs TEMP. RANGE 3) o • HC Types PART NUMBER ( C) PACKAGE /Sub- - 2V to 6V Operation CD54HC161F3A -55 to 125 16 Ld CERDIP ject - High Noise Immunity: N = 30%, N = 30% of V IL IH CC (High at V = 5V CD54HC163F3A -55 to 125 16 Ld CERDIP CC Speed • HCT Types CD54HCT163F3A -55 to 125 16 Ld CERDIP CMOS - 4.5V to 5.5V Operation CD74HC161E -55 to 125 16 Ld PDIP Logic - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) Preset- CD74HC161M -55 to 125 16 Ld SOIC IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V table l OL OH CD74HC161MT -55 to 125 16 Ld SOIC Counte Description CD74HC161M96 -55 to 125 16 Ld SOIC rs) The ’HC161, ’HCT161, ’HC163, and ’HCT163 are CD74HC163E -55 to 125 16 Ld PDIP /Autho presettable synchronous counters that feature look-ahead r () CD74HC163M -55 to 125 16 Ld SOIC carry logic for use in high-speed counting applications. The /Key- ’HC161 and ’HCT161 are asynchronous reset decade and CD74HC163MT -55 to 125 16 Ld SOIC words binary counters, respectively; the ’HC163 and ’HCT163 CD74HC163M96 -55 to 125 16 Ld SOIC devices are decade and binary counters, respectively, that (High are reset synchronously with the clock. Counting and Speed CD74HCT161E -55 to 125 16 Ld PDIP parallel presetting are both accomplished synchronously CMOS with the negative-to-positive transition of the clock. CD74HCT161M -55 to 125 16 Ld SOIC Logic A low level on the synchronous parallel enable input, SPE, CD74HCT161MT -55 to 125 16 Ld SOIC Preset- disables counting operation and allows data at the P0 to P3 CD74HCT161M96 -55 to 125 16 Ld SOIC inputs to be loaded into the counter (provided that the table setup and hold requirements for SPE are met). Counte CD74HCT163E -55 to 125 16 Ld PDIP All counters are reset with a low level on the Master Reset rs, CD74HCT163M -55 to 125 16 Ld SOIC input, MR. In the ’HC163 and ’HCT163 counters High (synchronous reset types), the requirements for setup and CD74HCT163MT -55 to 125 16 Ld SOIC Speed hold time with respect to the clock must be met. CD74HCT163M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
