CD74HC154M96G4 ,High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer 24-SOIC -55 to 125Featuresstate. The demultiplexing function is performed by using the• Two Enable Inputs to Facilita ..
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CD74HC157M ,High Speed CMOS Logic Quad 2-Input MultiplexersFeatures Description• Common Select Inputs The ’HC157, ’HCT157, ’HC158, and ’HCT158 are quad 2-inpu ..
CD74HC157M ,High Speed CMOS Logic Quad 2-Input MultiplexersFeatures Description• Common Select Inputs The ’HC157, ’HCT157, ’HC158, and ’HCT158 are quad 2-inpu ..
CD74HC157M96 ,High Speed CMOS Logic Quad 2-Input MultiplexersFeatures Description• Common Select Inputs The ’HC157, ’HCT157, ’HC158, and ’HCT158 are quad 2-inpu ..
CD74HC157M96 ,High Speed CMOS Logic Quad 2-Input MultiplexersMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CJ78L15 , Three-terminal positive voltage regulator
CJ78L15 , Three-terminal positive voltage regulator
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CJ78L18 , Three-terminal positive voltage regulator
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CJ78M06 , Three-terminal positive voltage regulator
CD74HC154M96G4
High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer
CD54HC154, CD74HC154, CD54HCT154, CD74HCT154 SCHS152D High-Speed CMOS Logic September 1997 - Revised June 2004 4- to 16-Line Decoder/Demultiplexer A High on either enable input forces the output into the High Features state. The demultiplexing function is performed by using the • Two Enable Inputs to Facilitate Demultiplexing and four input lines, A0 to A3, to select the output lines Y0 to Cascading Functions Y15, and using one enable as the data input while holding [ /Title • Fanout (Over Temperature Range) the other enable low. (CD74 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads HC154 Ordering Information - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads , o o • Wide Operating Temperature Range . . . -55 C to 125 C TEMP. RANGE D74 C o PART NUMBER ( C) PACKAGE • Balanced Propagation Delay and Transition Times HCT15 CD54HC154F3A -55 to 125 24 Ld CERDIP • Significant Power Reduction Compared to LSTTL 4) Logic ICs CD54HCT154F3A -55 to 125 24 Ld CERDIP /Sub- • HC Types ject CD74HC154E -55 to 125 24 Ld PDIP - 2V to 6V Operation (High CD74HC154EN -55 to 125 24 Ld PDIP - High Noise Immunity: N = 30%, N = 30%of V at IL IH CC Speed V = 5V CC CD74HC154M -55 to 125 24 Ld SOIC CMOS • HCT Types Logic CD74HC154M96 -55 to 125 24 Ld SOIC - 4.5V to 5.5V Operation 4-to-16 CD74HCT154E -55 to 125 24 Ld PDIP - Direct LSTTL Input Logic Compatibility, Line V = 0.8V (Max), V = 2V (Min) IL IH CD74HCT154EN -55 to 125 24 Ld PDIP Decod ≤ 1µA at V , V - CMOS Input Compatibility, I l OL OH CD74HCT154M -55 to 125 24 Ld SOIC er/Dem Description CD74HCT154M96 -55 to 125 24 Ld SOIC The ’HC154 and ’HCT154 are 4- to 16-line NOTE: When ordering, use the entire part number. The suffix 96 decoders/demultiplexers with two enable inputs, E1 and E2. denotes tape and reel. Pinout CD54HC154, CD54HCT154 (CERDIP) CD74HC154, CD74HCT154 (PDIP, SOIC) TOP VIEW Y0 1 24 V CC Y1 2 23 A0 Y2 3 22 A1 Y3 4 21 A2 Y4 5 20 A3 Y5 6 19 E2 Y6 7 18 E1 Y7 8 17 Y15 Y8 9 16 Y14 Y9 10 15 Y13 Y10 11 14 Y12 GND 12 13 Y11 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, 1
