CD74HC147M ,High Speed CMOS Logic 10-to-4 Line Priority EncoderCD54HC147, CD74HC147,CD74HCT147Data sheet acquired from Harris SemiconductorSCHS149FHigh-Speed CMOS ..
CD74HC147M ,High Speed CMOS Logic 10-to-4 Line Priority EncoderMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD74HC147M ,High Speed CMOS Logic 10-to-4 Line Priority EncoderCD54HC147, CD74HC147,CD74HCT147Data sheet acquired from Harris SemiconductorSCHS149FHigh-Speed CMOS ..
CD74HC147PWR ,High Speed CMOS Logic 10-to-4 Line Priority EncoderFeatures(Y0 to Y3). A priority is assigned to each input so that when[ /Title• Buffered Inputs and ..
CD74HC14E ,High Speed CMOS Logic Hex Schmitt-Triggered InvertersLogic DiagramnA nYVHVOV = V + - V -H T TVIV-V +T TV+V -T TVCCVV HIGNDVCCVOGNDFIGURE 3. HYSTERESIS D ..
CD74HC14M ,High Speed CMOS Logic Hex Schmitt-Triggered InvertersMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD74HC147E-CD74HC147M-CD74HC147PWR
High Speed CMOS Logic 10-to-4 Line Priority Encoder
CD54HC147, CD74HC147, CD74HCT147 SCHS149F High-Speed CMOS Logic September 1997 - Revised November 2003 10- to 4-Line Priority Encoder provide binary representation on the four active LOW inputs Features (Y0 to Y3). A priority is assigned to each input so that when [ /Title • Buffered Inputs and Outputs two or more inputs are simultaneously active, the input with (CD74 the highest priority is represented on the output, with input = 5V, • Typical Propagation Delay: 13ns at V CC HC147 line l having the highest priority. o 9 C = 15pF, T = 25 C L A , These devices provide the 10-line to 4-line priority encoding • Fanout (Over Temperature Range) CD74 function by use of the implied decimal “zero”. The “zero” is - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads HCT14 encoded when all nine data inputs are HIGH, forcing all four - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads outputs HIGH. 7) o o • Wide Operating Temperature Range . . . -55 C to 125 C /Sub- Ordering Information ject • Balanced Propagation Delay and Transition Times (High TEMP. RANGE • Significant Power Reduction Compared to LSTTL o PART NUMBER ( C) PACKAGE Speed Logic ICs CMOS CD54HC147F3A -55 to 125 16 Ld CERDIP • HC Types Logic - 2V to 6V Operation CD74HC147E -55 to 125 16 Ld PDIP 10-to-4 - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC147M -55 to 125 16 Ld SOIC at V = 5V Line CC CD74HC147MT -55 to 125 16 Ld SOIC Prior- • HCT Types ity - 4.5V to 5.5V Operation CD74HC147M96 -55 to 125 16 Ld SOIC - Direct LSTTL Input Logic Compatibility, Encode CD74HC147NSR -55 to 125 16 Ld SOP V = 0.8V (Max), V = 2V (Min) IL IH r) - CMOS Input Compatibility, I ≤ 1µA at V , V CD74HC147PW -55 to 125 16 Ld TSSOP l OL OH /Autho r () CD74HC147PWR -55 to 125 16 Ld TSSOP Description /Key- CD74HC147PWT -55 to 125 16 Ld TSSOP The ’HC147 and CD74HCT147 are high speed silicon-gate words CMOS devices and are pin-compatible with low power CD74HCT147E -55 to 125 16 Ld PDIP (High Schottky TTL (LSTTL). NOTE: When ordering, use the entire part number. The suffixes Speed The ’HC147 and CD74HCT147 9-input priority encoders 96 and R denote tape and reel. The suffix T denotes a CMOS accept data from nine active LOW inputs (l to l ) and small-quantity reel of 250. 1 9 Logic 10-to-4 Pinout Line Prior- CD54HC147 (CERDIP) CD74HC147 (PDIP, SOIC, SOP, TSSOP) ity CD74HCT147 (PDIP, TSSOP) Encode TOP VIEW r, High I4 1 16 V CC Speed I5 2 15 NC CMOS I6 3 14 Y3 Logic I7 4 13 I3 10-to-4 I8 5 12 I2 Line Y2 6 11 I1 Prior- Y1 7 10 I9 ity GND 8 9 Y0 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
