CD74HC126M96 ,High Speed CMOS Logic Quad Buffers with 3-State OutputsCD54HC126, CD74HC126,CD54HCT126, CD74HCT126Data sheet acquired from Harris SemiconductorSCHS144CHig ..
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CD74HC132E ,High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC132M ,High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC132M96 ,High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND GatesCD54HC132, CD74HC132,CD54HCT132, CD74HCT132Data sheet acquired from Harris SemiconductorSCHS145EHig ..
CD74HC132M96G4 ,High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND Gates 14-SOIC -55 to 125CD54HC132, CD74HC132,CD54HCT132, CD74HCT132Data sheet acquired from Harris SemiconductorSCHS145EHig ..
CJ7805 , Three-terminal positive voltage regulator
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CD74HC126E-CD74HC126M-CD74HC126M96
High Speed CMOS Logic Quad Buffers with 3-State Outputs
CD54HC126, CD74HC126, CD54HCT126, CD74HCT126 SCHS144C High-Speed CMOS Logic November 1997 - Revised September 2003 Quad Buffer, Three-State Features Description • Three-State Outputs The ’HC126 and ’HCT126 contain four independent three- state buffers, each having its own output enable input, which • Separate Output Enable Inputs [ /Title when “low” puts the output in the high-impedance state. • Fanout (Over Temperature Range) (CD74 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Ordering Information HC126 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads , TEMP. RANGE o o C to 125 C • Wide Operating Temperature Range . . . -55 o D74 C PART NUMBER ( C) PACKAGE HCT12 • Balanced Propagation Delay and Transition Times CD54HC126F3A -55 to 125 14 Ld CERDIP 6) • Significant Power Reduction Compared to LSTTL CD54HCT126F3A -55 to 125 14 Ld CERDIP /Sub- Logic ICs ject CD74HC126E -55 to 125 14 Ld PDIP • HC Types (High - 2V to 6V Operation CD74HC126M -55 to 125 14 Ld SOIC Speed - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC126MT -55 to 125 14 Ld SOIC at V = 5V CMOS CC CD74HC126M96 -55 to 125 14 Ld SOIC Logic • HCT Types Quad - 4.5V to 5.5V Operation CD74HCT126E -55 to 125 14 Ld PDIP Buffer, - Direct LSTTL Input Logic Compatibility, CD74HCT126M -55 to 125 14 Ld SOIC V = 0.8V (Max), V = 2V (Min) Three- IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V CD74HCT126MT -55 to 125 14 Ld SOIC l OL OH State) CD74HCT126M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC126, CD54HC126 (CERDIP) CD74HC126, CD74HC126 (PDIP, SOIC) TOP VIEW 1OE 1 14 V CC 1A 2 13 4OE 1Y 3 12 4A 2OE 4 11 4Y 2A 5 10 3OE 2Y 6 9 3A GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
