CD74HC123PWR ,High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with ResetCD54/74HC123, CD54/74HCT123,CD74HC423, CD74HCT423Data sheet acquired from Harris SemiconductorSCHS1 ..
CD74HC123PWR ,High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with ResetCD54/74HC123, CD54/74HCT123,CD74HC423, CD74HCT423Data sheet acquired from Harris SemiconductorSCHS1 ..
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CD74HC125M ,High Speed CMOS Logic Quad Buffers with 3-State OutputsFeatures Description• Three-State Outputs The ’HC125 and ’HCT125 contain 4 independent three-stateb ..
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CD74HC123-CD74HC123E-CD74HC123M-CD74HC123M96-CD74HC123M96G4-CD74HC123NSR-CD74HC123PW-CD74HC123PWG4-CD74HC123PWR
High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Reset
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 SCHS142F High-Speed CMOS Logic Dual Retriggerable September 1997 - Revised October 2003 Monostable Multivibrators with Resets Features Ordering Information • Overriding Reset Terminates Output Pulse o PART NUMBER TEMP. RANGE ( C) PACKAGE • Triggering From the Leading or Trailing Edge [ /Title CD54HC123F3A -55 to 125 16 Ld CERDIP Q Buffered Outputs • Q and (CD74 CD54HCT123F3A -55 to 125 16 Ld CERDIP • Separate Resets HC123 CD74HC123E -55 to 125 16 Ld PDIP • Wide Range of Output-Pulse Widths , • Schmitt Trigger on Both A and B Inputs CD74HC123M -55 to 125 16 Ld SOIC D74 C • Fanout (Over Temperature Range) CD74HC123MT -55 to 125 16 Ld SOIC HCT12 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads CD74HC123M96 -55 to 125 16 Ld SOIC 3, - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD74HC123NSR -55 to 125 16 Ld SOP CD74 o o • Wide Operating Temperature Range . . . -55 C to 125 C HC423 CD74HC123PW -55 to 125 16 Ld TSSOP • Balanced Propagation Delay and Transition Times , CD74HC123PWR -55 to 125 16 Ld TSSOP • Significant Power Reduction Compared to LSTTL D74 C Logic ICs CD74HC123PWT -55 to 125 16 Ld TSSOP HCT42 • HC Types CD74HC423E -55 to 125 16 Ld PDIP 3) - 2V to 6V Operation CD74HC423M -55 to 125 16 Ld SOIC = 30%, N = 30%of V at /Sub- - High Noise Immunity: N IL IH CC V = 5V CD74HC423MT -55 to 125 16 Ld SOIC CC ject • HCT Types CD74HC423M96 -55 to 125 16 Ld SOIC (High - 4.5V to 5.5V Operation Speed CD74HC423NSR -55 to 125 16 Ld SOP - Direct LSTTL Input Logic Compatibility, CD74HCT123E -55 to 125 16 Ld PDIP V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V CD74HCT123M -55 to 125 16 Ld SOIC l OL OH Description CD74HCT123MT -55 to 125 16 Ld SOIC The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are CD74HCT123M96 -55 to 125 16 Ld SOIC dual monostable multivibrators with resets. They are all CD74HCT423E -55 to 125 16 Ld PDIP retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the CD74HCT423MT -55 to 125 16 Ld SOIC 423 types do not have this feature. An external resistor (R ) X CD74HCT423M96 -55 to 125 16 Ld SOIC and an external capacitor (C ) control the timing and the X NOTE: When ordering, use the entire part number. The suffixes 96 accuracy for the circuit. Adjustment of Rx and C provides a X and R denote tape and reel. The suffix T denotes a small-quantity wide range of output pulse widths from the Q and Q reel of 250. terminals. Pulse triggering on the A and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses. Once triggered, the output pulse width may be extended by retriggering inputs A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A) and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A, B, and R) must be terminated high or low. The minimum value of external resistance, Rx is typically 5kΩ. The minimum value external capacitance, CX, is 0pF. The calculation for the pulse width is t = 0.45 R C at W X X V = 5V. CC CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
