CD74HC03M ,High Speed CMOS Logic Quad 2-Input NAND Gates with Open DrainCD54HC03, CD74HC03,CD54HCT03, CD74HCT03Data sheet acquired from Harris SemiconductorSCHS126DHigh-Sp ..
CD74HC03M ,High Speed CMOS Logic Quad 2-Input NAND Gates with Open DrainFeatures Description• Buffered Inputs The ’HC03 and ’HCT03 logic gates utilize silicon gate CMOStec ..
CD74HC03M96 ,High Speed CMOS Logic Quad 2-Input NAND Gates with Open DrainMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC03MT ,High Speed CMOS Logic Quad 2-Input NAND Gates with Open DrainFeatures Description• Buffered Inputs The ’HC03 and ’HCT03 logic gates utilize silicon gate CMOStec ..
CD74HC04E ,High Speed CMOS Logic Hex InvertersFeatures Description• Buffered Inputs The CD54HC04, CD54HCT04, CD74HC04 andCD74HCT04 logic gates ut ..
CD74HC04M ,High Speed CMOS Logic Hex InvertersMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CIUH11D66 , INVERTER
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CD74HC03E-CD74HC03M-CD74HC03M96-CD74HC03MT
High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain
CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 SCHS126D High-Speed CMOS Logic February 1998 - Revised September 2003 Quad 2-Input NAND Gate with Open Drain Features Description • Buffered Inputs The ’HC03 and ’HCT03 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL = 5V, • Typical Propagation Delay: 8ns at V [ /Title CC gates with the low power consumption of standard CMOS o C = 15pF, T = 25 C L A (CD74H integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally as well as • Output Pull-up to 10V C03, pin compatible with the standard LS logic family. CD74H • Fanout (Over Temperature Range) These open drain NAND gates can drive into resistive loads CT03) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads to output voltages as high as 10V. Minimum values of R L - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads /Subject required versus load voltage are shown in Figure 2. o o (High • Wide Operating Temperature Range . . . -55 C to 125 C Ordering Information Speed • Balanced Propagation Delay and Transition Times CMOS TEMP. RANGE • Significant Power Reduction Compared to LSTTL o Logic PART NUMBER ( C) PACKAGE Logic ICs Quad 2- CD54HC03F3A -55 to 125 14 Ld CERDIP • HC Types Input CD54HCT03F3A -55 to 125 14 Ld CERDIP - 2V to 6V Operation - High Noise Immunity: N = 30%, N = 30% of V CD74HC03E -55 to 125 14 Ld PDIP IL IH CC at V = 5V CC CD74HC03M -55 to 125 14 Ld SOIC • HCT Types CD74HC03MT -55 to 125 14 Ld SOIC - 4.5V to 5.5V Operation CD74HC03M96 -55 to 125 14 Ld SOIC - Direct LSTTL Input Logic Compatibility, CD74HCT03E -55 to 125 14 Ld PDIP V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V CD74HCT03M -55 to 125 14 Ld SOIC l OL OH CD74HCT03MT -55 to 125 14 Ld SOIC CD74HCT03M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC03, CD54HCT03 (CERDIP) CD74HC03, CD74HCT03 (PDIP, SOIC) TOP VIEW 1A 1 14 V CC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
