CD74HC02M96 ,High Speed CMOS Logic Quad 2-Input NOR GatesLogic DiagramnAnB2CD54HC02, CD74HC02, CD54HCT02, CD74HCT02Absolute
CD74HC02M96G4 ,High Speed CMOS Logic Quad 2-Input NOR Gates 14-SOIC -55 to 125CD54HC02, CD74HC02,CD54HCT02, CD74HCT02Data sheet acquired from Harris SemiconductorSCHS125CHigh-Sp ..
CD74HC03E ,High Speed CMOS Logic Quad 2-Input NAND Gates with Open DrainMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC03M ,High Speed CMOS Logic Quad 2-Input NAND Gates with Open DrainCD54HC03, CD74HC03,CD54HCT03, CD74HCT03Data sheet acquired from Harris SemiconductorSCHS126DHigh-Sp ..
CD74HC03M ,High Speed CMOS Logic Quad 2-Input NAND Gates with Open DrainFeatures Description• Buffered Inputs The ’HC03 and ’HCT03 logic gates utilize silicon gate CMOStec ..
CD74HC03M96 ,High Speed CMOS Logic Quad 2-Input NAND Gates with Open DrainMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD74HC02E-CD74HC02M-CD74HC02M96-CD74HC02M96G4
High Speed CMOS Logic Quad 2-Input NOR Gates
CD54HC02, CD74HC02, CD54HCT02, CD74HCT02 SCHS125C High-Speed CMOS Logic March 1998 - Revised September 2003 Quad Two-Input NOR Gate Features Description • Buffered Inputs The ’HC02 and ’HCT02 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL = 5V, • Typical Propagation Delay: 7ns at V [ /Title CC gates with the low power consumption of standard CMOS o C = 15pF, T = 25 C L A (CD74H integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin • Fanout (Over Temperature Range) C02, compatible with the standard LS logic family. - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads CD74H - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CT02) Ordering Information o o • Wide Operating Temperature Range . . . -55 C to 125 C /Subject o PART NUMBER TEMP. RANGE ( C) PACKAGE (High • Balanced Propagation Delay and Transition Times Speed CD54HC02F3A -55 to 125 14 Ld CERDIP • Significant Power Reduction Compared to LSTTL CMOS Logic ICs CD54HCT02F3A -55 to 125 14 Ld CERDIP Logic • HC Types CD74HC02E -55 to 125 14 Ld PDIP Quad - 2V to 6V Operation CD74HC02M -55 to 125 14 Ld SOIC Two- - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CC CD74HC02MT -55 to 125 14 Ld SOIC • HCT Types CD74HC02M96 -55 to 125 14 Ld SOIC - 4.5V to 5.5V Operation CD74HCT02E -55 to 125 14 Ld PDIP - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) IL IH CD74HCT02M -55 to 125 14 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HCT02MT -55 to 125 14 Ld SOIC CD74HCT02M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
