CD74HC00M96 ,High Speed CMOS Logic Quad 2-Input NAND GatesFeatures Description• Buffered Inputs The CD54HC00, CD74HC00, CD54HCT00, andCD74HCT00 logic gates u ..
CD74HC00M96 ,High Speed CMOS Logic Quad 2-Input NAND GatesFeatures Description• Buffered Inputs The CD54HC00, CD74HC00, CD54HCT00, andCD74HCT00 logic gates u ..
CD74HC00M96E4 ,High Speed CMOS Logic Quad 2-Input NAND Gates 14-SOIC -55 to 125CD54HC00, CD74HC00,CD54HCT00, CD74HCT00Data sheet acquired from Harris SemiconductorSCHS116CHigh-Sp ..
CD74HC00M96G4 ,High Speed CMOS Logic Quad 2-Input NAND Gates 14-SOIC -55 to 125Maximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC02E ,High Speed CMOS Logic Quad 2-Input NOR GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC02M ,High Speed CMOS Logic Quad 2-Input NOR GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CIUH11D66 , INVERTER
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CD74HC00-CD74HC00E-CD74HC00EE4-CD74HC00M-CD74HC00M96-CD74HC00M96E4-CD74HC00M96G4
High Speed CMOS Logic Quad 2-Input NAND Gates
CD54HC00, CD74HC00, CD54HCT00, CD74HCT00 SCHS116C High-Speed CMOS Logic January 1998 - Revised September 2003 Quad 2-Input NAND Gate Features Description • Buffered Inputs The CD54HC00, CD74HC00, CD54HCT00, and CD74HCT00 logic gates utilize silicon gate CMOS = 5V, • Typical Propagation Delay: 7ns at V [ /Title CC technology to achieve operating speeds similar to LSTTL o C = 15pF, T = 25 C L A (CD54 gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 • Fanout (Over Temperature Range) HC00, LSTTL loads. The 74HCT logic family is functionally pin - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads CD54 compatible with the standard 74LS logic family. - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads HCT00 o o Ordering Information • Wide Operating Temperature Range . . . -55 C to 125 C , D74 C • Balanced Propagation Delay and Transition Times TEMP. RANGE o HC00, PART NUMBER ( C) PACKAGE • Significant Power Reduction Compared to LSTTL CD74 Logic ICs CD54HC00F3A -55 to 125 14 Ld CERDIP HCT00 CD54HCT00F3A -55 to 125 14 Ld CERDIP • Alternate Source is Philips/Signetics ) CD74HC00E -55 to 125 14 Ld PDIP • HC Types Sub- / - 2V to 6V Operation CD74HC00M -55 to 125 14 Ld SOIC - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC00MT -55 to 125 14 Ld SOIC at V = 5V CC CD74HC00M96 -55 to 125 14 Ld SOIC • HCT Types CD74HCT00E -55 to 125 14 Ld PDIP - 4.5V to 5.5V Operation CD74HCT00M -55 to 125 14 Ld SOIC - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) IL IH CD74HCT00MT -55 to 125 14 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HCT00M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC00, CD54HCT00, (CERDIP) CD74HC00, CD74HCT00 (PDIP, SOIC) TOP VIEW 1A 1 14 V CC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
